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| 型號： | SII0680A |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI to IDE/ATA |
| 中文描述： | PCI到IDE / ATA的 |
| 文件頁數(shù)： | 74/124頁 |
| 文件大小： | 820K |
| 代理商： | SII0680A |
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SiI0680A PCI to IDE/ATA
Data Sheet
9.7.5
PCI Bus Master2 – IDE0
Address Offset: 10
H
Access Type: Read/Write
Reset Value: 0x0008_xx00
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
74
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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Software
Reserved
P
R
P
This register defines the second PCI bus master register for IDE Channel #0 in the SiI 0680A. The system must access these
register bits through this address to enable the Large Block Transfer Mode.
The register bits are defined below.
Bit [31:29]
: (R) These bits are copy of PCI Bus Master IDE1 bits [23:21].
Bit [28]
: IDE1 Watchdog (R ) . This bit is a copy of bit 12 in IDE1 Task File Timing + Configuration + Status
register. Refer to chapter 9.7.47 for detail information.
Bit [27]
: IDE1 Buffer empty (R). This bit set indicates IDE1 FIFO is empty.
Bit [26
:24]: (R) These bits are copy of PCI Bus Master IDE1 bits [18:16].
Bit [23]
: PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
indicate that both IDE channels can operate as PCI bus master at any time.
Bit [22]
: PBM DMA Cap 1 (R/W) – PCI Bus Master DMA Capable – Device 1. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [21]
: PBM DMA Cap 0 (R/W) – PCI Bus Master DMA Capable – Device 0. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [20]
: IDE0 Watchdog (R ) : This bit is a copy of bit 12 in IDE0 Task File Timing + Configuration + Status
register. Refer to chapter 9.7.33 for detail information.
Bit [19]
: IDE0 Buffer empty (R). This bit set indicates IDE0 FIFO is empty.
Bit [18]
: IDE0 DMA Comp (R/W1C) – IDE0 DMA Completion Interrupt. During write DMA operation, This bit set
indicates that the IDE0 interrupt has been asserted and all data has been written to system memory. During
Read
DMA,
This
bit
set
indicates
that
This bit must be W1C by software when set during DMA operation (bit 0 is set). During normal operation, this bit
reflects IDE0 interrupt line.
Bit [17]
: PBM Error (R/W1C) – PCI Bus Master Error – IDE0. This bit set indicates that a PCI bus error
occurred while the SiI 0680A was bus master. Additional information is available in the PCI Status register in PCI
Configuration space.
Bit [16]
: PBM Active (R) – PCI Bus Master Active – IDE0. This bit set indicates that the SiI 0680A is currently
active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data transfers have
completed or PBM Enable bit is not set.
Bit[15]
: IDE Watchdog Timer Status ( R ) – This bit is an Ored result of bit 12 in IDE1 Task File Timing +
Configuration + Status and bit 12 of IDE0 Task File Timing + Configuration + Status registers. When set indicates
that either IDE0 or IDE1 Watchdog timer has expired.
Bit[14]
: IDE1 Interrupt Status ( R ) – This bit is a copy of Bit[18] IDE1 DMA Completion Interrupt in PCI Bus
Master – IDE1.
Bit [13:08]
: Software Data (R/W) – System Software Data Storage. This bit field is used for read/write data
storage by the system. The properties of this bit field are detailed below.
the
IDE0
interrupt
has
been
asserted.
Bit Location
Default
Description
[13:12]
XX
B
Not cleared by any reset
[11:10]
00
B
Cleared by PCI reset
[09:08]
XX
B
Cleared only by a D0-D3 power state change
Table 9-9: Software Data Byte, Base Address 5, Offset 10
H
Bit [07:04]
: Reserved (R). This bit field is reserved and returns zeros on a read.
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