
Silicon Image, Inc.
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
63
9.2 Internal Register Space – Base Address 0
These registers are 32-bits wide and define the internal operation of the SiI 0680A. The access types are defined as follows:
R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O space.
Register Name
Address
Offset
31
16
15
00
Access
Type
00
H
IDE0 TF Starting
Sector Number
IDE0 TF Sector
Count
IDE0 TF Features
IDE0 TF Error
IDE0 TF Data
R/W
04
H
IDE0 TF
Command+Status
IDE0 TF
Device+Head
IDE0 TF
Cylinder High
IDE0 TF Cylinder
Low
R/W
Table 9-2: SiI 0680A Internal Register Space – Base Address 0
9.2.1
Address Offset: 00
H
Access Type: Read/Write
Reset Value: 0x0000_0000
IDE0 Task File Register 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE0 Task File Starting Sector
Number
IDE0 Task File Sector Count
IDE0 Task File Features (W)
IDE0 Task File Error (R)
IDE0 Task File Data
This register defines one of the IDE Channel #0 Task File registers in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset 80
H
. See Section 9.7.25 for bit definitions.
9.2.2
Address Offset: 04
H
Access Type: Read/Write
Reset Value: 0x0000_0000
IDE0 Task File Register 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE0 Task File Command + Status
IDE0 Task File Device+Head
IDE0 Task File Cylinder High
IDE0 Task File Cylinder Low
This register defines one of the IDE Channel #0 Task File registers in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset 84
H
. See Section 9.7.26 for bit definitions.