參數(shù)資料
型號： SII0680A
廠商： Silicon Image, Inc.
英文描述： PCI to IDE/ATA
中文描述： PCI到IDE / ATA的
文件頁數(shù)： 4/124頁
文件大?。?/td> 820K
代理商： SII0680A
SiI0680A PCI to IDE/ATA
Data Sheet
9.1.8
Base Address Register 3.......................................................................................................................................51
9.1.9
Base Address Register 4.......................................................................................................................................51
9.1.10
Base Address Register 5.....................................................................................................................................52
9.1.11
Subsystem ID – Subsystem Vendor ID................................................................................................................52
9.1.12
Expansion ROM Base Address ...........................................................................................................................53
9.1.13
Capabilities Pointer..............................................................................................................................................53
9.1.14
Max Latency – Min Grant – Interrupt Pin – Interrupt Line ....................................................................................53
9.1.15
Configuration .......................................................................................................................................................54
9.1.16
Software Data Register........................................................................................................................................54
9.1.17
Power Management Capabilities .........................................................................................................................54
9.1.18
Power Management Control + Status..................................................................................................................55
9.1.19
PCI Bus Master – IDE0........................................................................................................................................55
9.1.20
PRD Table Address – IDE0.................................................................................................................................56
9.1.21
PCI Bus Master – IDE1........................................................................................................................................56
9.1.22
PRD Table Address – IDE1.................................................................................................................................56
9.1.23
Data Transfer Mode – IDE0.................................................................................................................................57
9.1.24
Data Transfer Mode – IDE1.................................................................................................................................57
9.1.25
System Configuration Status – Command...........................................................................................................57
9.1.26
System Software Data Register...........................................................................................................................58
9.1.27
FLASH Memory Address – Command + Status ..................................................................................................58
9.1.28
FLASH Memory Data...........................................................................................................................................58
9.1.29
EEPROM Memory Address – Command + Status ..............................................................................................59
9.1.30
EEPROM Memory Data.......................................................................................................................................59
9.1.31
IDE0 Task File Timing + Configuration + Status..................................................................................................59
9.1.32
IDE0 PIO Timing..................................................................................................................................................60
9.1.33
IDE0 DMA Timing................................................................................................................................................60
9.1.34
IDE0 UDMA Timing .............................................................................................................................................60
9.1.35
IDE1 Task File Timing + Configuration + Status..................................................................................................61
9.1.36
IDE1 PIO Timing..................................................................................................................................................61
9.1.37
IDE1 DMA Timing................................................................................................................................................61
9.1.38
IDE1 UDMA Timing .............................................................................................................................................62
9.2
Internal Register Space – Base Address 0 ............................................................................................ 63
9.2.1
IDE0 Task File Register 0......................................................................................................................................63
9.2.2
IDE0 Task File Register 1......................................................................................................................................63
9.3
Internal Register Space – Base Address 1 ............................................................................................ 64
9.3.1
IDE0 Task File Register 2......................................................................................................................................64
9.4
Internal Register Space – Base Address 2 ............................................................................................ 65
9.4.1
IDE1 Task File Register 0......................................................................................................................................65
9.4.2
IDE1 Task File Register 1......................................................................................................................................65
9.5 Internal Register Space – Base Address 3................................................................................................ 66
9.5.1 IDE1 Task File Register 2..........................................................................................................................................66
9.6 Internal Register Space – Base Address 4................................................................................................ 67
9.6.1 PCI Bus Master – IDE0 .............................................................................................................................................67
9.6.2 PRD Table Address – IDE0.......................................................................................................................................67
9.6.3 PCI Bus Master – IDE1 .............................................................................................................................................68
9.6.4 PRD Table Address – IDE1.......................................................................................................................................68
9.7 Internal Register Space – Base Address 5................................................................................................ 69
9.7.1
PCI Bus Master – IDE0..........................................................................................................................................71
9.7.2
PRD Table Address – IDE0...................................................................................................................................72
9.7.3
PCI Bus Master – IDE1..........................................................................................................................................73
9.7.4
PRD Table Address – IDE1...................................................................................................................................73
9.7.5
PCI Bus Master2 – IDE0........................................................................................................................................74
9.7.6
PCI Bus Master2 – IDE1........................................................................................................................................75
9.7.7
PRD Address – IDE0.............................................................................................................................................76
9.7.8
PCI Bus Master Byte Count – IDE0.......................................................................................................................76
9.7.9
PRD Address – IDE1.............................................................................................................................................76
9.7.10
PCI Bus Master Byte Count – IDE1.....................................................................................................................77
9.7.11
FIFO Valid Byte Count and Control – IDE0..........................................................................................................77
9.7.12
FIFO Valid Byte Count and Control – IDE1..........................................................................................................78
9.7.13
System Configuration Status – Command...........................................................................................................79
9.7.14
System Software Data Register...........................................................................................................................79
9.7.15
FLASH Memory Address – Command + Status ..................................................................................................80
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0069-C
4
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