- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365565 > SII0680A (Silicon Image, Inc.) PCI to IDE/ATA PDF資料下載
參數(shù)資料
| 型號： | SII0680A |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI to IDE/ATA |
| 中文描述： | PCI到IDE / ATA的 |
| 文件頁數(shù)： | 73/124頁 |
| 文件大小： | 820K |
| 代理商： | SII0680A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁當(dāng)前第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁
Silicon Image, Inc.
9.7.3
PCI Bus Master – IDE1
Address Offset: 08
H
Access Type: Read/Write
Reset Value: 0x0000_0000
SiI0680A PCI to IDE/ATA
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0069-C
73
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
P
Reserved
P
P
R
I
P
P
Reserved
Reserved
P
R
P
This register defines the PCI bus master register for IDE Channel #1 in the SiI 0680A. The register bits are defined below.
Bit [31:24]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [23]
: PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
indicate that both IDE channels can operate as PCI bus master at any time.
Bit [22]
: PBM DMA Cap 1 (R/W) – PCI Bus Master DMA Capable – Device 1. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [21]
: PBM DMA Cap 0 (R/W) – PCI Bus Master DMA Capable – Device 0. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [20:19]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [18]
: IDE1 DMA Comp (R/W1C) – IDE1 DMA Completion Interrupt. During write DMA operation, this bit set
indicates that the IDE1 interrupt has been asserted and all data has been written to system memory. During
Read
DMA,
this
bit
set
indicates
that
This bit must be W1C by software when set during DMA operation (bit 0 is set). During normal operation, this bit
reflects IDE1 interrupt line.
Bit [17]
: PBM Error (R/W1C) – PCI Bus Master Error – IDE1. This bit set indicates that a PCI bus error
occurred while the SiI 0680A was bus master. Additional information is available in the PCI Status register in PCI
Configuration space.
Bit [16]
: PBM Active (R) – PCI Bus Master Active – IDE1. This bit set indicates that the SiI 0680A is currently
active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data transfers have
completed or PBM Enable bit is not set.
Bit [15:08]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [07:04]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [03]
: PBM Rd-Wr (R/W) – PCI Bus Master Read-Write Control. This bit is set to specify a DMA write
operation from IDE1 to system memory. This bit is cleared to specify a DMA read operation from system
memory to an IDE1 device.
Bit [02:01]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [00]
: PBM Enable (R/W) – PCI Bus Master Enable – IDE1. This bit is set to enable PCI bus master
operations for IDE Channel #1. PCI bus master operations can be halted by clearing this bit, but will erase all
state information in the control logic. If this bit is cleared while the PCI bus master is active, the operation will be
aborted and the data discarded. While this bit is set, accessing IDE1 Task File or PIO data registers will be
terminated with Target-Abort.
the
IDE1
interrupt
has
been
asserted.
9.7.4
Address Offset: 0C
H
Access Type: Read/Write
Reset Value: 0x0000_0000
PRD Table Address – IDE1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – IDE1
R
This register defines the PRD Table Address register for IDE Channel #1 in the SiI 0680A. The register bits are defined below.
Bit [31:02]
: PRD Table Address (R/W) – Physical Region Descriptor Table Address. This bit field defines the
Descriptor Table base address.
Bit [01:00]
: Reserved (R). This bit field is reserved and returns zeros on a read.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SiI0680ACL144 | PCI to IDE/ATA |
| SiI0680ACLU144 | PCI to IDE/ATA |
| SII0680 | SteelVine⑩ Host Controller |
| SII1000 | PanelLink Receivers |
| SII1151 | TELECOMMANDER USB(PC&Mac OS X) FOR DESKTOP ROVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII0680ACL144 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to IDE/ATA |
| SII0680ACLU144 | 制造商:Silicon Image Inc 功能描述:STEELVINE HOST CONTROLLER |
| SII1000 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receivers |
| SII100N06 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:NPT IGBT Modules |
| SII100N12 | 制造商:SIRECTIFIER 制造商全稱:Sirectifier Semiconductors 功能描述:NPT IGBT Modules |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。