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參數(shù)資料
| 型號： | SAA8200HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Ensation Base integrated wireless audio baseband |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 51/71頁 |
| 文件大?。?/td> | 298K |
| 代理商： | SAA8200HL |
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SAA8200HL_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 October 2005
51 of 71
Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
7.21.3
Timing specification
7.21.3.1
Play and stop with battery supply
A negative edge at pin DCDC_PLAY starts the DC-to-DC converter, see
Figure 22
. When
minimum supply voltages are detected for DCDC_OUT1V8 and DCDC_OUT3V3 by the
POR, the signal SUPPLY_OK is made logic 1. After about 1 ms signal RESET_B
becomes logic 1. When the supply voltages are correct the voltages to the application
control switches rises from V
BAT(DCDC)
to DCDC_OUT3V3. New negative edges on pin
DCDC_PLAY has no influence. When pin DCDC_STOP becomes HIGH the DC-to-DC
converter stops and directly the signal SUPPLY_OK becomes a logic 0.
The reference circuit, ring oscillator and the POR will be fed by V
DD(ALWAYS)
. Signal
RESET_B stays at logic 0 for about 1 ms for proper reset. Not shown in
Figure 22
is signal
CLK_STABLE, showing the moment for the core clock to become available to the
DC-to-DC converters. As soon as a stable core clock is detected the DC-to-DC converters
will switch to this clock in order to be in-phase with the DAC clock, which will minimize
interference into the audio signal. The SAA8200HL is started up when this has happened.
Fig 22. Play and stop with battery supply
V
BAT(DCDC),
DCDC_OUT3V3
0
DCDC_PLAY
DCDC_ON
SUPPLY_OK
RESET_B
～
1 ms
PLAYDET
DCDC_STOP
001aac010
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| SAA8200HL/N100,518 | 制造商:ST-Ericsson 功能描述:SAA8200HL Series Ensation Base Integrated Wireless Audio Baseband - LQFP-100 |
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| SA-A871-FREQ | 制造商:NEL 制造商全稱:Nel Frequency Controls,inc 功能描述:Positive ECL (PECL) |
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