參數(shù)資料
型號(hào)： SAA8200HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Ensation Base integrated wireless audio baseband
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù)： 44/71頁
文件大?。?/td> 298K
代理商： SAA8200HL
SAA8200HL_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 October 2005
44 of 71
Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
The SDAC has three modes of operation which are set by the control input bits
CTRL_INTI[21:20]:
Normal 1f
s
input mode used for input data rates between 8 kHz and 96 kHz using
sharp filter roll-off. De-emphasis (DEEM), volume control (VC) and mute (MT)
functions are all available in this mode
2f
s
input mode which may be used as:
–
Double speed input when the data rate is between 96 kHz and 200 kHz
–
A means to get slow roll-off by skipping the first half band filter (HB). In this mode
the de-emphasis (DEEM) is not available
8f
s
or DSD input mode, in which case the input is obtained form an external DSD
block. De-emphasis (DEEM), volume control (VC) and mute (MT) features are
unavailable in this mode.
7.20.1.7
Noise shaper
The 3rd-order noise shaper operates at either 128f
s
or 256f
s
depending on the mode of
operation defined by bits CTRL_INTI[23:20]. It shifts in-band quantization noise to
frequencies well above the audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved at low frequencies. The noise shaper output is
converted into an analog signal using a 4-bit switched resistor digital-to-analog converter.
7.20.1.8
SDAC
The 4-bit SDAC is based on a switched resistor architecture which is merely a controlled
voltage divider between the positive and negative reference supplies VREF_DACPand
VREF_DACN The 4-bit input data from the noise shaper is first decoded to a 15 level
thermometer code controlling the 15 taps of the converter. Added to the decoding is a
selectable Data Weighted Averaging (DWA) technique which guarantees that there is no
correlation between the input signal and the resistors used for that input signal.
After decoding and DWA the buffers connect the resistors to either the VREF_DACPor
VREF_DACN In doing this the reference voltage will be divided depending on the input
signal. The result is an analog output voltage with a rail-to-rail maximum output swing. The
output impedance of this DAC is approximately 1 k
. By applying an external capacitor of
3.3 nF to the line output (VOUTLINEL or VOUT_LINER) a low pass post filter is
introduced with a
3 dB roll off at 48 kHz (dimensioned for f
s
= 44.1 kHz). This will thus
reduce the 3rd order noise shaped output spectrum of the DAC to a noise spectrum
increasing with 2nd order. The value of this capacitor depends on the actual sample
frequency used.
7.20.1.9
Data weighting averaging
The SDAC features two DWA algorithms which can be selected independently for the left
(bit CTRL_DAC[1]) and right (bit CTRL_DAC[0]) channels. By setting these bits to a
logic 0 the uni-directional DWA algorithm is chosen which is best suited for good S/N
figures. By setting these bits to a logic 1 the bi-directional DWA algorithm is chosen which
is best for low distortion.
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