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參數(shù)資料
| 型號： | SAA8200HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Ensation Base integrated wireless audio baseband |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 31/71頁 |
| 文件大小： | 298K |
| 代理商： | SAA8200HL |
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SAA8200HL_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 October 2005
31 of 71
Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
7.12.1
I
2
S-bus inputs
Two I
2
S-bus inputs are provided, one of the two has dedicated pins, the second is
multiplexed using pin GPIO8 to GPIO10.
The I
2
S-bus inputs can be used in slave and master mode. In slave mode an external
I
2
S-bus source generates the bit clock and in master mode the SAA8200HL generates the
bit clock. In slave mode the bit clock arrives on pad I2SIN_x_BCK and is led to the CGU
input xt_I2SIN_x_BCK. This input should be switched directly to the CGU output
I2SIN_x_BCK which delivers the bit clock for the I
2
S-bus blocks.
In slave mode the audio PLL needs to lock on the incoming source. This can best be done
on the bit clock or on the word select. The bit clock is the preferred source because of its
higher frequency. The audio PLL has problems with locking on frequencies below
100 kHz. If the ratio between the bit clock and the sample frequency is not known, the
source word select can be used. The digital audio source will put out the data and the
word select on the negative edge of the bit clock and these will be sampled by the I
2
S-bus
block on the positive edge of the bit clock.
7.12.2
I
2
S-bus outputs
Two I
2
S-bus outputs are provided, both have dedicated data pins but the word select and
bit clock for both outputs are shared.
Depending on the application the source of the audio PLL could have an other input, then
the fractional dividers should be programmed to account for the difference in clock
frequency.
The I2S_OUT can only be used in master mode. For this reason the output enable of the
I2S_OUT_WS and I2S_OUT_BCK pads is always active in functional mode. The bit clock
generated by the CGU is inverted with respect to the word select, such that word select
changes on a negative edge of the bit clock.
7.13 Time stamp counters
A time stamp counter has been included to allow the software to get an indication of the
audio clocks.
The time stamp counter output is hardwired to seven EPICS7B input registers. Each input
register will be latched by another strobe signal. These strobe signals are generated by
the audio interfaces I2SIN, SPDIF, ADC, I2SOUT and DAC. This way each sample of each
audio source and sink can be labeled with a time stamp. The time stamp increases by one
every DSP clock tick, and will wrap-round at value (2
24
1).
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SAA8200HL/N100,518 | 制造商:ST-Ericsson 功能描述:SAA8200HL Series Ensation Base Integrated Wireless Audio Baseband - LQFP-100 |
| SAA8510EV1UM | 制造商:STMicroelectronics 功能描述: |
| SA-A870-FREQ | 制造商:NEL 制造商全稱:Nel Frequency Controls,inc 功能描述:Positive ECL (PECL) |
| SA-A871-FREQ | 制造商:NEL 制造商全稱:Nel Frequency Controls,inc 功能描述:Positive ECL (PECL) |
| SA-A877-FREQ | 制造商:NEL 制造商全稱:Nel Frequency Controls,inc 功能描述:Positive ECL (PECL) |
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