
SAA8200HL_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 October 2005
43 of 71
Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
time required for a full power-up or power-down equals 128 f
s
periods (raised cosine
function) plus 512 f
s
periods (DC ramp up/down) making 640 f
s
periods or 14.5 ms for
f
s
= 44.1 kHz. The power-up and power-down function is illustrated in
Figure 12
.
7.20.1.4
Silence detection
The silence detection circuit counts the number of digital input samples equal to zero. It is
enabled by the control bit CTRL_INTI[30]. The number of zero samples before signalling
silence detected (bit CTRL_INTO[3] for left channel and bit CTRL_INTO[2] for right
channel) can be set by bits CTRL_INTI[29:28]. This feature is not used to control the
SDAC, it is simply a feature that can be used in the system.
7.20.1.5
Polarity control
The stereo output signal polarity of the C18INT can be changed by setting the
CTRL_INTI[26] to logic 1. Note that this single control bit affects both channels.
7.20.1.6
Digital upsampling filter
The interpolation from 1f
s
to 128f
s
is realized in four stages:
The first stage is a 99-tap half band filter (HB) which increases the sample rate from
1f
s
to 2f
s
and has a steep transition band to correct for the missing inherent filter
function of the SDAC.
The second stage is a 31-tap FIR filter which increases the data rate from 2f
s
to 8f
s
,
scales the signal and compensates for the roll-off caused by the sample-and-hold
function prior to the noise shaper. For this filter three sets of coefficients can be
chosen realizing three different transfer characteristics.
The third stage is a simple hardware linear interpolator (LIN) function that increases
the sample rate from 8f
s
to 16f
s
and removes the 8f
s
component in the output
spectrum. The main reason for upsampling to 16f
s
is the fact that the SDAC only has a
first order roll-off function.
The fourth and last stage is a sample-and-hold function increasing the sample rate
from 16f
s
to a selectable 128f
s
or 256f
s
, depending on the actual input data rate. For
input sample rates between 8 kHz and 32 kHz the noise shaper and DAC must run on
256f
s
instead of the typical 128f
s
to avoid a significant noise increase in the audible
frequency band of 0 kHz to 20 kHz.
Fig 13. Interpolator data path
001aab468
normal
speed
double
speed
DSD
DEEM
2
HB
MT
VC
S&H
LIN
4
FIR
1f
s
2f
s
8f
s
16f
s
128f
s
or
256fs
2f
s
8f
s