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參數(shù)資料
| 型號： | SAA8200HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Ensation Base integrated wireless audio baseband |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 20/71頁 |
| 文件大?。?/td> | 298K |
| 代理商： | SAA8200HL |
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SAA8200HL_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 October 2005
20 of 71
Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
0x02B8
0x02BC
0x02C0
0x02C4
0x02C8
0x2CC
0x2D0
0x02D4
0x02D8
0x02DC
0x02E0
0x02E4
0x02E8
0x02EC
0x02F0
0x2F4
0x02F8
0x02FC
0x300
0x0304
0x0308
0x030C
0x0310
0x0C00
0x0C04
0x0C08
0xC0C
0x0C10
0x0C14
0x0C18
0x0C1C
0x0C20
0x0C24
0x0C28
0x0C2C
0x0C30
0x0C34
0xC38
0x0C3C
0x0C40
0x0C44
ESR_CR_CLK_OUT1
ESR_CR_CLK_OUT2
ESR_SRI_CHCLK
BCR_LP0
BCR_HP0
FDC_SPD_SYSCLK
FDC_SYSCLK_DIV4
FDC_UART_UCLK
FDC_DEBOUNCE_PCLK
FDC_ADC_CLK
FDC_DIO_PCLK
FDC_AUDIO_PCLK
FDC_FRAMESYNCREF
FDC_CR_I2SIN_2_BCK
FDC_CR_I2SIN_1_BCK
FDC_CR_I2SOUT_BCK
FDC_I2S_WS
FDC_SDAC_NS_CLK
FDC_AUDIO_SYSCLK
FDC_DCDC_CONVERTER_CLK fractional divider control for DC-to-DC converter clock
FDC_CR_CLK_OUT1
fractional divider control for crystal output 1 from pad
FDC_CR_CLK_OUT2
fractional divider control for crystal output 2 from pad
FDC_SRI_CHCLK
fractional divider control for SRI channel clock
CNF_POWERMODE
power-down CGU
CNF_WD_BARK
watchdog bark register
reserved
reserved
OSC_ON
activate crystal oscillator
OSC_BYPASS
bypass crystal oscillator
CNF_UART_RST_N
reset for UART
CNF_I2SIN_1_RST_N
reset for I2S input 1
CNF_I2SIN_2_RST_N
reset for I2S input 2
CNF_I2SOUT_1_RST_N
reset for I2S output 1
CNF_I2SOUT_2_RST_N
reset for I2S output 2
CNF_DEC_RST_N
reset for decimation filter
CNF_INT_RST_N
reset for interpolation filter
CNF_SPDIF_RST_N
reset for SPDIF
CNF_EPICS7B_RST_N
reset for EPICS7B
CNF_DIO2VPB0_RST_N
reset for VPB0 bridge
CNF_DIO2VPB1_RST_N
reset for UART VPB bridge
CNF_MS_I2C_RST_N
reset for M/S I
2
C-bus
enable fraction divider for crystal output 1 from pad
enable fraction divider for crystal output 2 from pad
enable fraction divider for SRI channel clock
base control register for system PLL clock
base control register for audio PLL clock
fractional divider control for system clock
fractional divider control for 0.25
×
f
s
system clock
fractional divider control for UART clock
fractional divider control for DEBOUNCE bus clock
fractional divider control for control ADC system clock
fractional divider control for DIO interface clock
fractional divider control for audio bus clock
fractional divider control for SRI frame sync reference
fractional divider control for I2SIN_2 bit clock
fractional divider control for I2SIN_1 bit clock
fractional divider control for I2SOUT bit clock
fractional divider control for I2S word select
fractional divider control for SDAC new sample
fractional divider control for audio system clock
Table 11:
Base address Offset
VPB0 bridge interface description
…continued
Key
Description
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| SAA8200HL/N100,518 | 制造商:ST-Ericsson 功能描述:SAA8200HL Series Ensation Base Integrated Wireless Audio Baseband - LQFP-100 |
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| SA-A871-FREQ | 制造商:NEL 制造商全稱:Nel Frequency Controls,inc 功能描述:Positive ECL (PECL) |
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