參數(shù)資料
型號: SAA8200HL
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Ensation Base integrated wireless audio baseband
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù): 23/71頁
文件大?。?/td> 298K
代理商: SAA8200HL
SAA8200HL_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 October 2005
23 of 71
Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
7.3 Clock generation unit
The Clock Generation Unit (CGU) generates all clock signals required for the
SAA8200HL, it contains:
A crystal oscillator
For low power mode the internal DC-to-DC converter clock can be used as system
clock
An audio PLL to generate audio sample frequencies
A system PLL to generate the clocks for the VPB bus and the DSP subsystem
A clock switch block
A configuration register block
A reset and power block.
An 11.2896 MHz oscillator or an external 11.025 MHz clock (provided by the TEA7000)
can be used in combination with the two PLLs and the external clocks to generate the
system frequencies.
All PLLs are programmed with the registers in the register configuration block.
0x0014
0x0018
0x0020
0x0024
0x0028
IOC_MODE0_SET
IOC_MODE0_RESET
IOC_MODE1
IOC_MODE1_SET
IOC_MODE1_RESET
set mode 0
reset mode 0
load mode 1
set mode 1
reset mode 1
audio configuration
I
2
S-bus format settings
I
2
S-bus multiplexer settings
SPDIF status
SPDIF interrupt enable
SPDIF interrupt status
SPDIF interrupt clear
audio DAC input interpolation filter control
audio DAC output interpolation filter control
audio DAC control
audio ADC amplifiers control
audio ADC control
audio ADC input decimation filter control
audio ADC output decimation filter control
EPICS7B interrupt request
power-down control ADC
DC-to-DC converter adjust output voltage (1.8 V)
DC-to-DC converter adjust output voltage (3.3 V)
DC-to-DC converter clock stable signal
0x7000
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
I2S_FORMAT_SETTINGS
I2S_MUX_SETTINGS
SPDIF_STATUS
SPDIF_IRQ_EN
SPDIF_IRQ_STATUS
SPDIF_IRQ_CLEAR
SDAC_CTRL_INTI
SDAC_CTRL_INTO
SDAC_SETTINGS
SADC_CTRL_SDC
SADC_CTRL_ADC
SADC_CTRL_DECI
SADC_CTRL_DECO
E7B_IRQ
PD_ADC10B
SET_DCDC1V8_ADJUST
SET_DCDC3V3_ADJUST
DCDC_CLOCKSTABLE
Table 11:
Base address Offset
VPB0 bridge interface description
…continued
Key
Description
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