
SAA8200HL_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 October 2005
21 of 71
Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
0x0C48
0x0C4C
0x0C50
0x0C54
0x0C58
0x0C5C
0x0C60
0x0C64
0x0C68
0x0C6C
0x0C70
0x0C74
0x0C78
0x0C7C
0x0C80
0x0C84
0x0C88
0x0C8C
0x0C90
0x0C94
0x0C98
0x0C9C
0x0CA0
0x0CA4
0x0CA8
0x0CAC
0x0CB0
0x0CB4
CNF_SRI _RST_N
CNF_RSC_RST_N
CNF_SRI_I2C_RST_N
CNF_AD10BIT_RST_N
CNF_FSL_RST_N
CNF_GCC_RST_N
CNF_AD10BIT_PRST_N
HP0_FIN_SELECT
HP0_MDEC
HP0_NDEC
HP0_PDEC
HP0_MODE
HP0_STATUS
HP0_ACK
HP0_REQ
HP0_INSELR
HP0_INSELI
HP0_INSELP
HP0_SELR
HP0_SELI
HP0_SELP
LP0_FIN_SELECT
LP0_PWD
LP0_BYPASS
LP0_LOCK
LP0_DIRECT
LP0_MSEL
LP0_PSEL
reset for serial radio interface
reset for Reed-Solomon codec
reset for SRI I
2
C-bus
reset for control ADC
reset for frame sync lock
reset for gated channel clock
preset for control ADC
audio clock PLL input select
audio clock PLL M divider
audio clock PLL N divider
audio clock PLL P divider
audio clock PLL mode
audio clock PLL status
audio clock PLL acknowledge
audio clock PLL change request
audio clock PLL input bandwidth selection
audio clock PLL input bandwidth selection
audio clock PLL input bandwidth selection
audio clock PLL input bandwidth selection
audio clock PLL input bandwidth selection
audio clock PLL input bandwidth selection
system clock PLL input select
system clock PLL power-down
system clock PLL bypass
system clock PLL in-lock
system clock PLL direct CCO control
system clock PLL M divider
system clock PLL P divider
SRI I
2
C-bus
receive FIFO
transmit FIFO
status register
control register
clock divisor high
clock divisor low
I
2
C-bus address
slave transmit FIFO
control ADC
ADC data channel 0
ADC data channel 1
ADC data channel 2
0x1000
0x0000
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0028
RX
TX
STS
CTL
CLKHI
CLKLO
ADDR
TXS
0x2000
0x0000
0x0004
0x0008
ADC_R0
ADC_R1
ADC_R2
Table 11:
Base address Offset
VPB0 bridge interface description
…continued
Key
Description