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參數(shù)資料
| 型號： | SAA8200HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Ensation Base integrated wireless audio baseband |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 25/71頁 |
| 文件大?。?/td> | 298K |
| 代理商： | SAA8200HL |
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SAA8200HL_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 October 2005
25 of 71
Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
7.3.3
System PLL
The DSP-PLL works in normal operating mode with feedback-divider and with
post-divider, this means that the base for the clock signal is the current controlled
oscillator (f
out
= f
cco/P
), running on 264.6 MHz. The output clock (f
out
) is divided-by-2 to
generate a 132.3 MHz clock.
Features:
Integrated PLL with on-chip Current Controlled Oscillator (CCO), no external
components for clock generation
Functional down to 1.2 V (with reduced frequency range)
10 MHz to 25 MHz input frequency range
9.75 MHz to 160 MHz selectable output frequency with 50 % output duty cycle
156 MHz to 320 MHz CCO frequency range
Power-down mode
Input clock bypass mode
Lock detector available
Current consumption maximum 1 mA
Maximum peak cycle-to-cycle output jitter = 300 ps.
7.4 Serial radio interface
Features:
Interface between wireless audio baseband processor and wireless audio radio IC
Bi-directional 3-wire serial interface
Can be locked to audio sample frequencies
Enables end-to-end audio clock synchronization
Supports master and slave modes
Supports continuous and high speed repetitive burst mode
Control of the radio IC is handled via a separate I
2
C-bus interface
Designed for minimal interference with the radio chip.
7.5 SRI I
2
C-bus
The I
2
C-bus master/slave module provides a serial interface that meets the I
2
C-bus
specification and supports all transfer modes from and to the I
2
C-bus. It supports the
following functionality:
It supports both the normal mode (100 kHz SCL) and the fast mode (400 kHz SCL)
It has word (32-bit) access from the CPU side
Interrupt generation on received or sent byte (and some special cases).
The purpose of the SRI I
2
C-bus is to allow the download of program code from an external
EEPROM at start-up, configuration and monitoring of the radio IC (TEA7000), and
storage/retrieval of application specific parameters in an external data EEPROM.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SAA8200HL/N100,518 | 制造商:ST-Ericsson 功能描述:SAA8200HL Series Ensation Base Integrated Wireless Audio Baseband - LQFP-100 |
| SAA8510EV1UM | 制造商:STMicroelectronics 功能描述: |
| SA-A870-FREQ | 制造商:NEL 制造商全稱:Nel Frequency Controls,inc 功能描述:Positive ECL (PECL) |
| SA-A871-FREQ | 制造商:NEL 制造商全稱:Nel Frequency Controls,inc 功能描述:Positive ECL (PECL) |
| SA-A877-FREQ | 制造商:NEL 制造商全稱:Nel Frequency Controls,inc 功能描述:Positive ECL (PECL) |
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