
SAA8200HL_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 October 2005
12 of 71
Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
The interrupts and connection order are described in
Table 7
.
Table 6:
Register name
DSP
PC
SR1
SR2
RTI_STACK
IO_DIR
IO_MODE
CR
EIR
Interrupt controller
INTC_POL
INTC_MODE
INTC_MASK
INTC_STATUS
INTC_TEST
INTC_SWCLR
INTC_SLCT
DMA controller
DMAC_IC
Control registers description
Address
R/W
Description
Reset
0x0 FFFF
0x0 FFFE
0x0 FFFD
0x0 FFFC
0x0 FFFB
0x0 FFFA
0x3 FFFF
0x3 FFFE
W
W
W
W
W
W
W
W
program counter register
status register 1
status register 2
interrupt stack register
configuration register 1
configuration register 2
control register I/O mapped
EPICS7B instruction register
undefined
undefined
undefined
undefined
0x00 0000
0x00 0FFD
0x00 0000
0x00 0000
0x0 FFF9
0x0 FFF8
0x0 FFF7
0x0 FFF6
0x0 FFF5
0x0 FFF4
0x0 FFF3
W
W
W
R
W
W
W
polarity select
mode select
mask
status
test
software clear
user flag
0x03 FFFF
0x03 FFFF
0x03 FFFF
undefined
0x00 0001
0x00 0000
0x00 0000
0x0 FFF2
R
IRQ counter value
0x00 0000
Table 7:
Interrupt flag
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Interrupt flags
Symbol
FI_DMAC
FI_SRI_DMA_RX_RDY SRI RX DMA block transfer interrupt
FI_FLSTART
FSL start interrupt
FI_EVENTROUTER
event router interrupt
FI_SRI_DMA_TX_RDY SRI TX DMA block transfer interrupt
FI_I2SIN_1
I
2
S-bus input 1 interrupt
FI_I2SIN_2
I
2
S-bus input 2 interrupt
FI_SPDIF
SPDIF input interrupt
FI_ADC
ADC input interrupt
FI_DACALL
I
2
S-bus and DAC outputs interrupt
FI_RSC_ENCRDY
RSC encoder ready interrupt
FI_RSC_DECRDY
RSC decoder ready interrupt
FI_RSC_DMARDY
RSC DMA block transfer ready interrupt
FI_VPB0
VPB0 interrupt
FI_VBP1
VPB1 interrupt
FI_UART
UART interrupt
FI_I2C_DMARDY
I
2
C-bus M/S DMA block transfer interrupt
FI_FSLFAST
FSL fast interrupt
Description
DMAC interrupt