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| 型號： | Pentium III cpu with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| 中文描述： | 奔騰III處理器的移動模塊連接器2（絲裂霉素2）（帶移動模塊連接器2奔三處理器） |
| 文件頁數(shù)： | 35/64頁 |
| 文件大小： | 773K |
| 代理商： | PENTIUM III CPU WITH MOBILE |
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Pentium
III Processor Mobile Module MMC-2
245304-003
Datasheet
29
Table 19
describes the signal quality specifications at the processor core for the PSB clock (BCLK)
signal.
Figure 4
describes the signal quality waveforms for the PSB clock at the processor core pins
For proper signal termination, refer to the
“
Clocking Guidelines
”
section in the
Mobile Pentium
III
Processor/440BX AGPset Recommended Design and Debug Practices (RDDP-A) 100 MHz Rev.
2.0
(SC-2760).
NOTES:
1. On the rising edge of BCLK, there must be a minimum overshoot to 2.0V. The clock must rise monotonically
between V
and 2.0V and fall monotonically between V
and
V
.
2. These specifications apply only when BCLK is running. See
Table 17
for the DC specifications when BCLK is
stopped. BCLK may not be above V
or below V
for more than 50% of the clock cycle.
3. The rising edge ringback voltage specified is the minimum (rising) absolute voltage that the BCLK signal can
dip back to after it passes the V
(rising) voltage limits.The falling edge ringback voltage specified
is the maximum (falling) absolute voltage that the BCLK signal can dip back to after it passes the
V
(falling) voltage limits.
4. Specifications labeled N/A are not available.
Figure 4. BCLK Waveform at the Processor Core Pins
Table 19. BCLK Signal Quality AC Specifications at the Processor Core
T#
Parameter
Min
Max
Unit
Notes
V1
V
IL,BCLK
-0.3
0.7
V
Notes 1, 4
V2
V
IH,BCLK
1.7
2.625
V
Notes 1, 4
V3
V
IN
Absolute Voltage Range
-0.7
3.5
V
Undershoot, Overshoot, Note 2
V4
Rising Edge Ringback
1.7
N/A
V
Absolute Value, Notes 3, 4
V5
Falling Edge Ringback
N/A
0.7
V
Absolute Value, Notes 3, 4
BCLK Rising/Falling Slew Rate
0.8
4.0
V/nS
V1
MAX
V3
MAX
V2
MIN
V4
V3
MIN
V5
V0012-00
T3
T6
T4
T5
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