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| 型號： | Pentium III cpu with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| 中文描述： | 奔騰III處理器的移動模塊連接器2（絲裂霉素2）（帶移動模塊連接器2奔三處理器） |
| 文件頁數(shù)： | 13/64頁 |
| 文件大?。?/td> | 773K |
| 代理商： | PENTIUM III CPU WITH MOBILE |
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Pentium
III Processor Mobile Module MMC-2
245304-003
Datasheet
7
3.1.3
AGP Signals
Table 3
provides descriptions of the AGP interface signals.
Table 3. AGP Signal Descriptions
Name
Type
Voltage
Description
GAD[31:]
I/O
AGP
V_3
AGP Address/Data
: The standard AGP address and data lines. This
bus functions in the same way as the PCI AD[31:0] bus. The address
is driven with FRAME# assertion, and data is driven or received in
following clocks.
GC/BE[3:0]#
I/O
AGP
V_3
AGP Command/Byte Enable:
This bus carries the command
information during AGP cycles when PIPE# is used. During an AGP
write, this bus contains byte enable information. The command is
driven with FRAME# assertion, and byte enables corresponding to
supplied or requested data are driven on the following clocks.
GFRAME#
I/O
AGP
V_3
AGP Frame:
GFRAME# is not used during AGP transactions. This
signal remains deasserted by an internal pullup resistor. Assertion
indicates the address phase of a PCI transfer. Negation indicates that
the cycle initiator desires one more data transfer.
GDEVSEL#
I/O
AGP
V_3
AGP Device Select
: This signal provides the same function as PCI
DEVSEL#, and it is not used during AGP transactions. The 82443BX
Host Bridge system controller drives this signal when a PCI initiator is
attempting to access DRAM. DEVSEL# is asserted at medium
decode time.
GIRDY#
I/O
AGP
V_3
AGP Initiator Ready
: GIRDY# indicates the AGP-compliant target is
ready to provide all write data for the current transaction. This signal
is asserted when the initiator is ready for a data transfer.
GTRDY#
I/O
AGP
V_3
AGP Target Ready
: This signal indicates the AGP-compliant master
is ready to provide all write data for the current transaction. GTRDY#
is asserted when the target is ready for a data transfer.
GSTOP#
I/O
AGP
V_3
AGP Stop:
This signal provides the same function as PCI STOP#,
and it is not used during AGP transactions. GSTOP# is asserted by
the target to request the master to stop the current transaction.
GREQ#
I
AGP
V_3
AGP Request:
AGP master requests for AGP.
GGNT#
O
AGP
V_3
AGP Grant:
GGNT
#
provides the same function as on PCI.
Additional information is provided on the ST[2:0] bus.
PCI Grant: Permission is given to the master to use PCI.
GPAR
I/O
AGP
V_3
AGP Parity
: A single parity bit is provided over GAD[31:0] and GC/
BE[3:0]. This signal is not used during AGP transactions.
PIPE#
I
AGP
V_3
Pipelined Request:
PIPE#
is asserted by the current master to
indicate that a full-width address is to be queued by the target. The
master queues one request each rising clock edge while PIPE# is
asserted.
SBA[7:0]
I
AGP
V_3
Sideband Address
: This bus provides an additional conduit to pass
address and commands to the 82443BX Host Bridge System
Controller from the AGP master.
RBF#
I
AGP
V_3
Read Buffer Full
: Indicates if the master is ready to accept
previously requested, low-priority read data.
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