- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369993 > Pentium III cpu with mobile (Intel Corp.) Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動(dòng)模塊連接器2奔III處理器) PDF資料下載
參數(shù)資料
| 型號(hào)： | Pentium III cpu with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動(dòng)模塊連接器2奔III處理器) |
| 中文描述： | 奔騰III處理器的移動(dòng)模塊連接器2（絲裂霉素2）（帶移動(dòng)模塊連接器2奔三處理器） |
| 文件頁數(shù)： | 31/64頁 |
| 文件大?。?/td> | 773K |
| 代理商： | PENTIUM III CPU WITH MOBILE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
Pentium
III Processor Mobile Module MMC-2
245304-003
Datasheet
25
Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition to
the Stop Grant state or the Quick Start state, where a Stop Grant Acknowledge bus cycle will be
issued. Deasserting STPCLK# will cause the processor to return to the Auto Halt state without
issuing a new Halt bus cycle.
The SMI# (System Management Interrupt) is recognized in the Auto Halt state. The return from the
SMI handler can be to either the Normal state or the Auto Halt state. See the
Intel
Architecture
Software Developer's Manual, Volume III: System Programmer's Guide
for more information. No
Halt bus cycle is issued when returning to the Auto Halt state from System Management Mode
(SMM).
The FLUSH# signal is serviced in the Auto Halt state. After flushing the on-chip, the processor
will return to the Auto Halt state without issuing a Halt bus cycle. Transitions in the A20M# and
PREQ# signals are recognized while in the Auto Halt state.
4.4.1.3
Stop Grant State
Intel mobile modules do not support the Stop Grant state.
In desktop systems, the processor enters this mode with the assertion of the STPCLK# signal when
it is configured for Stop Grant state (via the A15# strapping option). The processor is still able to
respond to snoop requests and latch interrupts. Latched interrupts will be serviced when the
processor returns to the Normal state. Only one occurrence of each interrupt event will be latched.
A transition back to the Normal state can be made by the deassertion of the STPCLK# signal, or the
occurrence of a stop break event (a BINIT#, FLUSH#, or RESET# assertion).
The processor will return to the Stop Grant state after the completion of a BINIT# bus initialization
unless STPCLK# has been deasserted. RESET# assertion will cause the processor to immediately
initialize itself. However, the processor will stay in the Stop Grant state after initialization until
STPCLK# is deasserted. If the FLUSH# signal is asserted, the processor will flush the on-chip
caches and return to the Stop Grant state. A transition to the Sleep state can be made by the
assertion of the SLP# signal.
While in the Stop Grant state, assertions of SMI#, INIT#, INTR, and NMI (or LINT[1:0]) will be
latched by the processor. These latched events will not be serviced until the processor returns to the
Normal state. Only one of each event will be recognized upon return to the Normal state.
4.4.1.4
Quick Start State
This is a mode entered by the processor with the assertion of the STPCLK# signal when it is
configured for the Quick Start state (via the A15# strapping option). In the Quick Start state the
processor is only capable of acting on snoop transactions generated by the PSB priority device.
Because of its snooping behavior, Quick Start can only be used in single processor configurations.
A transition to the Deep Sleep state can be made by stopping the clock input to the processor. A
transition back to the Normal state (from the Quick Start state) is made only if the STPCLK# signal
is deasserted.
While in this state the processor is limited in its ability to respond to input. It is incapable of
latching any interrupts, servicing snoop transactions from symmetric bus masters, or responding to
FLUSH# and BINIT# assertions. In the Quick Start state, the processor will not respond properly
to any input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal changes,
then the behavior of the processor will be unpredictable. No serial interrupt messages may begin or
be in progress while the processor is in the Quick Start state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| pentium III processor | 32 bit Processor Mobile Module(32 位帶移動(dòng)模塊處理器) |
| Pentium OverDrive Processor | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動(dòng)處理器) |
| pentium pro processor | Pentium Pro Processor with 1MB L2 Cache at 200MHZ(1兆比特L2高速緩存頻率200兆赫茲處理器) |
| pentium processor with MMX | 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。