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參數(shù)資料
| 型號(hào)： | Pentium III cpu with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動(dòng)模塊連接器2奔III處理器) |
| 中文描述： | 奔騰III處理器的移動(dòng)模塊連接器2（絲裂霉素2）（帶移動(dòng)模塊連接器2奔三處理器） |
| 文件頁數(shù)： | 12/64頁 |
| 文件大小： | 773K |
| 代理商： | PENTIUM III CPU WITH MOBILE |
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Pentium
III Processor Mobile Module MMC-2
6
Datasheet
245304-003
3.1.2
Memory Signal Description
Table 2
provides descriptions of the memory interface signals.
Table 2. Memory Signal Descriptions
Name
Type
Voltage
Description
MECC[7:0]
I/O
CMOS
V_3
Memory ECC Data:
These signals carry Memory ECC data during
access to DRAM.
ECC is not supported on the mobile module.
CSA[5:O]#
O
CMOS
V_3
Chip Select (SDRAM):
These pins activate the SDRAMs.
SDRAM
accepts any command when its CS# pin is active low.
DQMA[7:0]
O
CMOS
V_3
Input/Output Data Mask (SDRAM):
These pins act as synchronized
output enables during a read cycle and as a byte mask during a write
cycle.
MAB[9:0]#
MAB[10]
MAB[12:11]#
MAB[13]
O
CMOS
V_3
Memory Address (SDRAM):
This is the row and column address for
DRAM.
The 82443BX Host Bridge system controller has two identical
sets of address lines (MAA and MAB#). The mobile module supports
only the MAB set of address lines. For additional addressing features,
please refer to the
Intel
440BX AGPSet: 82443BX Host Bridge/
Controller Datasheet (Order Number: 290633-001).
MWEA#
O
CMOS
V_3
Memory Write Enable (SDRAM):
MWEA# should be used as the
write enable for the memory data bus.
SRASA#
O
CMOS
V_3
SDRAM Row Address Strobe (SDRAM):
When active low, this
signal latches Row Address on the positive edge of the clock. This
signal also allows Row access and pre-charge.
SCASA#
O
CMOS
V_3
SDRAM Column Address Strobe (SDRAM):
When active low, this
signal latches Column Address on the positive edge of the clock.
This
signal also allows Column access.
CKE[5:0]
O
CMOS
V_3
SDRAM Clock Enable (SDRAM):
SDRAM clock enable pin. When
these signals are deasserted, SDRAM enters power-down mode.
Each row is individually controlled by its own clock enable.
MD[63:0]
O
CMOS
V_3
Memory Data:
These signals are connected to the DRAM data bus.
They are not terminated on the mobile module.
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