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參數(shù)資料
| 型號(hào)： | Pentium III cpu with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動(dòng)模塊連接器2奔III處理器) |
| 中文描述： | 奔騰III處理器的移動(dòng)模塊連接器2（絲裂霉素2）（帶移動(dòng)模塊連接器2奔三處理器） |
| 文件頁數(shù)： | 21/64頁 |
| 文件大?。?/td> | 773K |
| 代理商： | PENTIUM III CPU WITH MOBILE |
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Pentium
III Processor Mobile Module MMC-2
245304-003
Datasheet
15
3.1.9
ITP and JTAG Pins
Table 9
provides descriptions of the ITP and JTAG signals, which the system manufacturer can use
to implement a JTAG chain and an ITP port if desired.
NOTE:
FS_RESET# and FS_PRDY# are pulled up to VTT inside the mobile Pentium III processor core.
3.1.10
Miscellaneous Pins
Table 10
provides descriptions of the miscellaneous signal pins.
Table 9. ITP and JTAG Pins
Name
Type
Voltage
Description
TDO
O
V_CPUPU
JTAG Test Data Out:
A serial output port. TAP instructions and data
are shifted out of the processor from this port.
TDI
I
VTT
JTAG Test Data In:
A serial input port. TAP instructions and data are
shifted into the processor from this port.
TMS
I
VTT
JTAG Test Mode Select:
Controls the TAP controller change
sequence.
TCLK
I
VTT
JTAG Test Clock:
Testability clock for clocking the JTAG boundary
scan sequence.
TRST#
I
VTT
JTAG Test Reset:
Asynchronously resets the TAP controller in the
processor.
FS_PREQ#
I
VTT
Debug Mode Request:
Driven by the ITP
–
makes request to enter
debug mode.
FS_PRDY#
O
VTT
Debug Mode Ready:
Driven by the processor
–
informs the ITP that
the processor is in debug mode.
FS_RESET#
O
VTT
Processor Reset:
Processor reset status to the ITP.
VTT
O
VTT
GTL+ Termination Voltage:
The POWERON pin uses VTT on the
ITP debug port to determine when target system is on. The
POWERON pin is pulled up using a 1-K
resistor to VTT. Other ITP
signals might use this power rail for pullup.
Table 10. Miscellaneous Pin Descriptions
Name
Type
Number
Description
Module ID[3:0]
O
CMOS
4
Module Revision ID
: These pins track the revision level of the mobile
module. A 100-K pullup resistor to V_3S must be placed on the system
electronics for these signals. See
Section 8.0
for more detail.
Ground
I
45
Ground
Reserved
RSVD
33
Unallocated Reserved pins.
All Reserved pins must not be connected.
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