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參數(shù)資料
| 型號： | Pentium III cpu with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| 中文描述： | 奔騰III處理器的移動模塊連接器2（絲裂霉素2）（帶移動模塊連接器2奔三處理器） |
| 文件頁數(shù)： | 28/64頁 |
| 文件大?。?/td> | 773K |
| 代理商： | PENTIUM III CPU WITH MOBILE |
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Pentium
III Processor Mobile Module MMC-2
22
Datasheet
245304-003
is always device #0, AD11 will never be asserted during PCI configuration cycles as an IDSEL.
The 82443BX reserves AD12 for the AGPbus. Thus, AD13 is the first available address line usable
as an IDSEL. Intel recommends that AD18 be used by the PIIX4E/M.
4.3.4
AGP Interface
The 82443BX Host Bridge system controller is compliant with the
AGP Interface Specification
Revision 2.0
, which supports an asynchronous AGP interface coupling to the 82443BX core
frequency. The AGP interface can achieve real data throughput in excess of 500 MB per second
using an AGP 2X graphics device. Actual bandwidth may vary depending on specific hardware
and software implementations.
4.4
Power Management
4.4.1
Clock Control Architecture
The clock control architecture has been optimized for notebook designs. The clock control
architecture consists of seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start,
HALT/Grant Snoop, Sleep, and Deep Sleep states. The Auto Halt state provides a low-power clock
state that can be controlled through the software execution of the HLT instruction. The Quick Start
state provides a very low-power, low-exit latency clock state that can be used for hardware
controlled "idle" states. The Deep Sleep state provides an extremely low-power state that can be
used for Power-On-Suspend states, which is an alternative to shutting off the processor
’
s power.
The exit latency of the Deep Sleep state is 30
μ
S in the mobile module. The Stop Grant state and
the Quick Start clock state are mutually exclusive. For example, a strapping option on signal A15#
chooses which state is entered when the STPCLK# signal is asserted. Strapping the A15# signal to
ground at Reset enables the Quick Start state. Otherwise, asserting the STPCLK# signal puts the
processor into the Stop Grant state.
Table 14
provides information on the clock control states and
Figure 3
illustrates the clock control
architecture. Performing state transitions not shown in
Figure 3
are neither recommended nor
supported.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| pentium III processor | 32 bit Processor Mobile Module(32 位帶移動模塊處理器) |
| Pentium OverDrive Processor | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動處理器) |
| pentium pro processor | Pentium Pro Processor with 1MB L2 Cache at 200MHZ(1兆比特L2高速緩存頻率200兆赫茲處理器) |
| pentium processor with MMX | 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器) |
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