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參數(shù)資料
| 型號： | Pentium III cpu with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| 中文描述： | 奔騰III處理器的移動模塊連接器2（絲裂霉素2）（帶移動模塊連接器2奔三處理器） |
| 文件頁數(shù)： | 34/64頁 |
| 文件大?。?/td> | 773K |
| 代理商： | PENTIUM III CPU WITH MOBILE |
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Pentium
III Processor Mobile Module MMC-2
28
Datasheet
245304-003
5.0
Electrical Specifications
The following section provides the electrical specifications for the Pentium
III
processor mobile
module.
5.1
System Bus Clock Signal Quality Specifications
The HCLK0 and BCLK signal names are used interchangeably.
5.1.1
BCLK DC Specifications
NOTE:
V
ILX,min
and V
IH,max
only apply when BCLK is stopped. BCLK should be stopped in the low state. See
Table 18
for the BCLK voltage range specifications when BCLK is running.
5.1.2
BCLK AC Specifications
NOTES:
1. All AC timings for GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25V. All CMOS
signals are referenced at 0.75V.
2. The internal core clock frequency is derived from the PSB clock. The PSB clock to core clock ratio is
determined during initialization and is predetermined by the Intel mobile module. The BCLK period allows a
+0.5 nS tolerance for clock driver variation.
3. This value is measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted
for as a component of BCLK skew between devices.
4. The clock driver
’
s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The -20.0 dB attenuation point, as measured into a 10.0-pF to a 2.0-pF load,
should be less than 500 kHz. This specification may be ensured by design characterization and/or measured
with a spectrum analyzer. See the
CK97 Clock Synthesizer/Driver Specification (OR-1089)
for further details.
5. These values are not 100% tested and are specified by design characterization as a clock driver
requirement.
6. Specifications labeled N/A are not available.
Table 17. BCLK DC Specifications
Symbol
Parameter
Min
Max
Unit
V
IL,BCLK
Input Low Voltage, BCLK
- 0.3
0.5
V
V
IH,BCLK
Input High Voltage, BCLK
2.0
2.625
V
Table 18. BCLK AC Specifications at the Processor Core Pins
T#
Parameter
Min
Nom
Max
Unit
Note
System Bus Frequency
N/A
100.0
N/A
MHz
Notes 5, 6
BCLK Period
N/A
10.0
N/A
nS
Notes 2, 5, 6
BCLK Period Stability
N/A
N/A
±
250
pS
Notes 3, 4, 5, 6
T3:
BCLK High Time
2.85
N/A
N/A
nS
At > 1.7V, Notes 5, 6
T4:
BCLK Low Time
2.55
N/A
N/A
nS
At > 0.7V, Notes 5, 6
T5:
BCLK Rise Time
0.175
N/A
0.875
nS
0.9V ~ 1.6V, Notes 5, 6
T6:
BCLK Fall Time
0.175
N/A
0.875
nS
1.6V ~ 0.9V, Notes 5, 6
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