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| 型號(hào)： | Pentium II 333 |
| 廠商： | Intel Corp. |
| 英文描述： | Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器) |
| 中文描述： | 而對(duì)整個(gè)處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器） |
| 文件頁(yè)數(shù)： | 39/50頁(yè) |
| 文件大小： | 1123K |
| 代理商： | PENTIUM II 333 |
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Pentium
II
Processor with On-Die Cache – Low-Power Module
Datasheet
39
With the circuit shown in Figure 8: t_delay = 5.53 ms; t_tran = 14.0 ms; and I_max = 146 mA.
Figure 9 shows a SPICE simulation of the circuit in Figure 8. To increase the reliability of tantalum
capacitors, use a slew-rate control circuit described in Figure 8 and voltage derate the capacitor
about 50 percent. That is, for a maximum input voltage of 18.0 V, use a 35.0-V, low ESR capacitor
with high ripple current capability. Place five, 22-μF/35-V capacitors on the baseboard, directly at
the V_DC pins of the processor module connector. Finally, the slew-rate control circuit should be
applied to every input power source to the system V_DC to provide the most protection. A
potential problem still exists if all power sources are “l(fā)ogically OR’ed” together at the PWR node.
For example, the system will immediately source current to the PWR node and V_DC if a 3X3
Li-Ion battery pack is powering the system (12.0 V at PWR) and the AC Adaptor (18.0 V) is
plugged into the system. This is because the slew-rate control is already on. Therefore, the slew-
rate control must be applied to every input power source to provide the most protection.
I
.
CtotalVpwr
t_ramp
Figure 9. Spice Simulation Using In-rush Protection (Example ONLY))
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