- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369993 > Pentium II 333 (Intel Corp.) Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器) PDF資料下載
參數(shù)資料
| 型號： | Pentium II 333 |
| 廠商： | Intel Corp. |
| 英文描述： | Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器) |
| 中文描述： | 而對整個處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器） |
| 文件頁數(shù)： | 15/50頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | PENTIUM II 333 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
Pentium
II
Processor with On-Die Cache – Low-Power Module
Datasheet
15
3.1.7
Power Management (7 Signals)
Table 7 lists the power management signals. The SM_CLK and SM_DATA signals refer to the
two-wire serial SMBus interface. Although this interface is currently used solely for the digital
thermal sensor, the SMBus contains reserved serial addresses for future use. See
“Thermal Sensor
Configuration Register” on page 41 for more details.
A20M#
I D
CMOS
V_CPUPU
Address Bit 20 Mask:
When enabled, this open-drain signal
causes the processor to emulate the address wraparound at one
MB, which occurs on the Intel 8086 processor.
SMI#
I D
CMOS
V_CPUPU
System Management Interrupt:
SMI# is an active low
synchronous output from the PIIX4E that is asserted in response to
one of many enabled hardware or software events.
The SMI# open-
drain signal can be an asynchronous input to the processor.
However, in this chip set SMI# is synchronous to PCLK.
STPCLK#
I D
CMOS
V_CPUPU
Stop Clock:
STPCLK# is an active low synchronous open-drain
output from the PIIX4E that is asserted in response to one of many
hardware or software events.
STPCLK# connects directly to the
processor and is synchronous to PCICLK.
When the processor
samples STPCLK# asserted, it responds by entering a low power
state (Quick Start). The processor will only exit this mode when this
signal is deasserted.
Table 6. Processor/PIIX4E Sideband Signal Descriptions (Sheet 2 of 2)
Name
Type
Voltage
Description
Table 7. Power Management Signal Descriptions
Name
Type
Voltage
Description
SUS_STAT1#
I
CMOS
V_3ALWAY
Suspend Status:
This signal connects to the SUS_STAT1#
output of PIIX4E. It provides information on host clock status and
is asserted during all suspend states.
VR_ON
I
CMOS
V_3
VR_ON:
Voltage regulator ON.
This 3.3V (5V tolerant) signal
controls the operation of the voltage regulator.
VR_ON should be
generated as a function of the PIIX4E SUSB# signal which is
used for controlling the “Suspend State B” voltage planes. This
signal should be driven by a digital signal with a rise/fall time of
less than or equal to 1 μs. Refer to “Voltage Signal Definition and
Sequencing” on page 33. (VIL (max)=0.4V, VIH (min)=3.0V).
VR_PWRGD
O
V_3
VR_PWRGD:
This signal is driven high by the module to indicate
that the voltage regulator is stable. The signal is pulled low using
a 100 K
resistor when inactive.
It can be used in some
combination to generate the system PWRGOOD signal.
BXPWROK
I
CMOS
V_3
Power OK to BX:
This signal must go active 1 ms after the V_3
power rail is stable, and 1 ms prior to deassertion of PCIRST#.
SM_CLK
I/O D
CMOS
V_3
Serial Clock:
This clock signal is used on the SMBus interface to
the digital thermal sensor.
SM_DATA
I/O D
CMOS
V_3
Serial Data:
Open-drain data signal on the SMBus interface to
the digital thermal sensor.
ATF_INT#
O D
CMOS
V_3
ATF Interrupt:
This signal is an open-drain output signal of the
digital thermal sensor.
V_3ALWAYS: 3.3 V supply. It is generated whenever V_DC is available and supplied to PIIX4E resume
well.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| pentium II cpu with mobile | pentium II processor With On-die Cache Mobile Module Connector 2 (MMC-2)(帶緩存和連接器2的奔II處理器) |
| pentium II cpu | Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) |
| pentium II processor | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| pentium II xeon processor | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。