Datasheet
3
Pentium
II
Processor with On-Die Cache – Low-Power Module
Contents
1.0
2.0
3.0
Introduction
..................................................................................................................7
Architecture Overview
.............................................................................................7
Connector Interface
...................................................................................................8
3.1
Signal Definitions...................................................................................................8
3.1.1
Signal List.................................................................................................9
3.1.2
Memory (109 Signals) ............................................................................10
3.1.3
AGP (60 Signals)....................................................................................11
3.1.4
PCI (58 Signals).....................................................................................12
3.1.5
Geyserville (4 Signals) ...........................................................................14
3.1.6
Processor/PIIX4E Sideband (8 Signals).................................................14
3.1.7
Power Management (7 Signals).............................................................15
3.1.8
Clock (9 Signals)....................................................................................16
3.1.9
Voltages (54 Signals).............................................................................17
3.1.10 ITP/JTAG (9 Signals) .............................................................................17
3.1.11 Miscellaneous (82 Signals) ....................................................................18
3.2
Connector Pin Assignments................................................................................18
3.3
Pin and Pad Assignments...................................................................................21
Functional Description
...........................................................................................22
4.1
Pentium
II
Processor With On-Die Cache – Low-Power Module......................22
4.2
L2 Cache.............................................................................................................22
4.3
The 82443BX Host Bridge/Controller..................................................................22
4.3.1
Memory Organization.............................................................................23
4.3.2
Reset Strap Options...............................................................................23
4.3.3
PCI Interface ..........................................................................................24
4.3.4
AGP Interface.........................................................................................24
4.4
Power Management............................................................................................24
4.4.1
Clock Control Architecture......................................................................24
4.4.2
Normal State ..........................................................................................26
4.4.3
Auto Halt State .......................................................................................26
4.4.4
Stop Grant State.....................................................................................26
4.4.5
Quick Start State ....................................................................................27
4.4.6
HALT/Grant Snoop State .......................................................................27
4.4.7
Sleep State.............................................................................................27
4.4.8
Deep Sleep State...................................................................................28
4.5
Typical POS/STR Power.....................................................................................28
4.6
Electrical Requirements ......................................................................................29
4.6.1
DC Requirements...................................................................................29
4.6.2
AC Requirements...................................................................................30
4.6.2.1 PSB Clock Signal Quality Specifications and
Measurement Guidelines ..........................................................30
4.7
Voltage Regulator................................................................................................32
4.7.1
Voltage Regulator Efficiency..................................................................32
4.7.2
Control of the Voltage Regulator............................................................33
4.7.2.1 Voltage Signal Definition and Sequencing ................................33
4.0