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參數(shù)資料
| 型號(hào)： | Pentium II 333 |
| 廠商： | Intel Corp. |
| 英文描述： | Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器) |
| 中文描述： | 而對(duì)整個(gè)處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器） |
| 文件頁數(shù)： | 16/50頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | PENTIUM II 333 |
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Pentium
II
Processor with On-Die Cache – Low-Power Module
16
Datasheet
3.1.8
Clock (9 Signals)
Table 8 lists the clock signals.
Table 8. Clock Signal Descriptions
Name
Type
Voltage
Description
PCLK
I
PCI
V_3
PCI Clock In:
PCLK is an input to the module and is one of the
system’s PCI clocks.
This clock is used by all of the 82443BX Host
Bridge/Controller logic in the PCI clock domain.
This clock is
stopped when the PIIX4E PCI_STP# signal is asserted and/or
during all suspend states.
HCLK[1:0]
I
CMOS
V_CLK
Host Clock In:
These clocks are inputs to the module from the
CK97-M clock source. The processor and the 82443BX Host
Bridge/Controller use HCLK[0]. This clock is stopped when the
PIIX4E CPU_STP# signal is asserted and/or during all suspend
states.
DCLKO
O
CMOS
V_3
SDRAM Clock Out:
A 66-MHz SDRAM clock reference generated
internally by the 82443BX Host Bridge/Controller onboard PLL. It
feeds an external buffer that produces multiple copies for the SO-
DIMMs.
DCLKRD
I
CMOS
V_CLK
SDRAM Read Clock:
Feedback reference from the SDRAM clock
buffer. The 82443BX Host Bridge/Controller uses this clock when
reading data from the SDRAM array. This signal is not implemented
on the module.
DCLKWR
I
CMOS
V_CLK
SDRAM Write Clock:
Feedback reference from the SDRAM clock
buffer. The 82443BX Host Bridge/Controller uses this clock when
writing data to the SDRAM array.
GCLKIN
I
CMOS
V_3
AGP Clock In:
The GCLKIN input is a feedback reference from the
GCLKO signal.
GCLKO
O
CMOS
V_3
AGP Clock Out:
This signal is generated by the 82443BX Host
Bridge/Controller onboard PLL from the HCLK0 host clock
reference. The frequency of GCLKO is 66 MHz. The GCLKO output
is used to feed both the PLL reference input pins on the 82443BX
Host Bridge/Controller and the AGP device. The board layout must
maintain complete symmetry on loading and trace geometry to
minimize AGP clock skew.
FQS
O
CMOS
V_CLK
Frequency Select:
This output signal provides the status of the
host clock frequency to the system electronics.
This signal is static
and is pulled either low or high to the V_CLK voltage supply through
a 10-K
resistor. This module is designed for the 66-MHz strapping
option shown below.
FQS=0 indicates 66 MHz
FQS=1 indicates 100 MHz (for future modules)
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