參數(shù)資料
型號(hào)： Pentium II 333
廠商： Intel Corp.
英文描述： Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器)
中文描述： 而對(duì)整個(gè)處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器）
文件頁(yè)數(shù)： 28/50頁(yè)
文件大?。?/td> 1123K
代理商： PENTIUM II 333
Pentium
II
Processor with On-Die Cache – Low-Power Module
28
Datasheet
4.4.8
Deep Sleep State
The Deep Sleep state is the lowest power mode the processor can enter while maintaining its
context. Stopping the BCLK input to the processor enters the Deep Sleep state, while it is in the
Sleep state or the Quick Start state. For proper operation, the BCLK input should be stopped in the
low state.
The processor will return to the Sleep state or the Quick Start state from the Deep Sleep state when
the BCLK input is restarted. Due to the PLL lock latency, there is a 30-ms delay after the clocks
have started before this state transition happens. PICCLK may be removed in the Deep Sleep state.
PICCLK should be designed to turn on when BCLK turns on when transitioning out of the Deep
Sleep state.
The input signal restrictions for the Deep Sleep state are the same as for the Sleep state, except that
RESET# assertion will result in unpredictable behavior.
4.5
Typical POS/STR Power
Table 17 shows the typical POS/STR power values.
Table 16. Clock State Characteristics
Clock State
Exit Latency
Processor
Power
Snooping
System Uses
Normal
N/A
Varies
Yes
Normal program execution.
Auto Halt
Approximately 10 bus clocks
1.2 W
Yes
S/W controlled entry idle
mode.
Stop Grant
1
10 bus clocks
1.2 W
Yes
H/W controlled entry/exit
throttling.
Quick Start
Through snoop
, to
HALT/Grant Snoop state:
immediate
Through STPCLK#
, to Normal
state: 10 bus clocks
0.5 W
Yes
H/W controlled entry/exit
throttling.
HALT/Grant
Snoop
A few bus clocks after the end
of snoop activity.
Not
specified
Yes
Supports snooping in the low
power states.
Sleep
1
To Stop Grant state 10 bus
clocks
0.5 W
No
H/W controlled entry/exit
desktop idle mode support.
Deep Sleep
30 ms
150 mW
No
H/W controlled entry/exit
powered-on suspend
support.
NOTES:
1. The module does not support the Sleep and Stop Grant clock control states.
2.
Not 100% tested. Specified at 50° C by design/characterization.
Table 17. POS/STR Power
State
Typical Module Power
POS
0.475 W
STR
0.018 W
NOTE:
These are average values of measurement and are guidelines only.
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