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參數(shù)資料
| 型號(hào)： | Pentium II 333 |
| 廠商： | Intel Corp. |
| 英文描述： | Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器) |
| 中文描述： | 而對(duì)整個(gè)處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器） |
| 文件頁數(shù)： | 35/50頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | PENTIUM II 333 |
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Pentium
II
Processor with On-Die Cache – Low-Power Module
Datasheet
35
4.7.3
Power Planes: Bulk Capacitance Requirements
In order to provide adequate filtering and in-rush current protection for any system design, bulk
capacitance is required. A small amount of bulk capacitance is supplied on the module. However,
in order to achieve proper filtering, additional capacitance should be placed on the system
electronics.
Table 24 details the bulk capacitance requirements for the system electronics.
Figure 5. Power-on Sequence Timing
POWER SEQUENCE TIMING
V_DC
1. PWROK on I/O board should be active on when VR_PWRGD is active and V_3S is good.
2. CPU_RST from I/O board should be active for a minimum of 6 ms after PWROK is active and PLL_STP# and CPU_STP# are
inactive. Note that PLL_STP# is an AND condition of RSMRST# and SUSB# on the PIIX4E/M.
3. V_DC >= 4.7V, V_5>=4.5V, V_3S>=3.0V.
4. V_CPUPU and V_CLK are generated on the Intel Module.
5. This is the 5V power supplied to the processor module connector. This should be the first 5V plane to power up.
6. VR_PWRGD is specified to its associated high/active by the module regulator within less than or equal to 6 ms max. after the
assertion of VR_ON.
V_3
V_5
VR_PWRGD
V_3S
VR_ON
0 MS MIN
0 MS MIN
0 MS MIN
6
3
V_CPUPU/
V_CLK
5
Table 24. Capacitance Requirement per Power Plane
Power Plane
Capacitance Requirements
ESR
Ripple Current
Rating
V_DC
100 μF, 0.1 μF, 0.01 μF
1
20 m
1 A-3.5 A
3
20% tolerance at 35 V
V_5
100 μF, 0.1 μF, 0.01 μF
1
100 m
1 A
20% tolerance at 10 V
V_3
470 μF, 0.1 μF, 0.01 μF
1
100 m
1 A
20% tolerance at 6 V
V_3S
100 μF, 0.1 μF, 0.01 μF
1
100 m
N/A
20% tolerance at 6 V
VCC_AGP
22 μF, 0.1 μF, 0.01 μF
1
100 m
1 A
20% tolerance at 6 V
V_CPUPU
2.2 μF, 8200 pF
1
N/A
N/A
20% tolerance at 6 V
V_CLK2
10 μF, 8200 pF
2
N/A
N/A
20% tolerance at 6 V
NOTES:
1. Placement of above capacitance requirements should be located near the connector.
2. V_CLK filtering should be located next to the system clock synthesizer.
3. Ripple current specification depends on V_DC input. For 5.0 V V_DC, a 3.5 A device is required. For V_DC
at 18 V or higher, 1 A is sufficient.
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