參數(shù)資料
型號(hào)： Pentium II 333
廠商： Intel Corp.
英文描述： Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器)
中文描述： 而對(duì)整個(gè)處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器）
文件頁數(shù)： 14/50頁
文件大小： 1123K
代理商： PENTIUM II 333
Pentium
II
Processor with On-Die Cache – Low-Power Module
14
Datasheet
3.1.5
Geyserville (4 Signals)
Table 5 lists the Geyserville signal definitions. The module does not support Geyserville
technology. This section is included for those wishing to design for compatibility with future
modules.
3.1.6
Processor/PIIX4E Sideband (8 Signals)
Table 6 lists the signals for the processor and the PIIX4E sideband signals. The voltage level for
these signals is determined by V_CPUPU.
Table 5. Geyserville Descriptions
Name
Type
Voltage
Description
G_LO/HI#
I
CMOS
V_3
Geyserville State Transition
: Generated by the PIIX4E, this signal
defines a Geyserville state change to the Geyserville state machine.
This signal is not implemented on the module.
G_CPU_STP#
I
CMOS
V_3
Geyserville CPU_STP#
: The CPU_STP# signal gated by the
Geyserville state machine becomes G_CPU_STP#. This signal is
not implemented on the module.
VRCHGNG#
O
CMOS
V_3
Voltage Changing
: A Geyserville state machine signal that indicates
that the actual state change is in progress – the VR setpoint has
changed and the VR is settling. When this signal deasserts, the new
state is sent to the processor. The system electronics will use this
signal to generate an SCI to force a transition out of deep sleep. This
signal is not implemented on the module.
G_SUS_STAT1#
O
CMOS
V_3
G_SUS_STAT1#:
The SUS_STAT1# signal gated by the Geyserville
control logic. G_SUS_STAT1# should be used in place of the
SUS_STAT1# signal in the system electronics design. This signal is
not implemented on the module.
Table 6. Processor/PIIX4E Sideband Signal Descriptions (Sheet 1 of 2)
Name
Type
Voltage
Description
FERR#
O
CMOS
V_CPUPU
Numeric Coprocessor Error:
This pin functions as a FERR#
signal supporting coprocessor errors. This signal is tied to the
coprocessor error signal on the processor and is driven by the
processor to the PIIX4E.
IGNNE#
I D
CMOS
V_CPUPU
Ignore Error:
This open-drain signal is connected to the Ignore
Error pin on the processor and is driven by the PIIX4E.
INIT#
I D
CMOS
V_CPUPU
Initialization:
INIT# is asserted by the PIIX4E to the processor for
system initialization. This signal is an open-drain.
INTR
I D
CMOS
V_CPUPU
Processor Interrupt:
INTR is driven by the PIIX4E to signal the
processor that an interrupt request is pending and needs to be
serviced. This signal is an open-drain.
NMI
I D
CMOS
V_CPUPU
Non-maskable Interrupt:
NMI is used to force a non-maskable
interrupt to the processor.
The PIIX4E ISA bridge generates a NMI
when either SERR# or IOCHK# is asserted, depending on how the
NMI Status and Control Register is programmed. This signal is an
open-drain.
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