參數(shù)資料
型號： Pentium II 333
廠商： Intel Corp.
英文描述： Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器)
中文描述： 而對整個(gè)處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器）
文件頁數(shù)： 11/50頁
文件大小： 1123K
代理商： PENTIUM II 333
Pentium
II
Processor with On-Die Cache – Low-Power Module
Datasheet
11
3.1.3
AGP (60 Signals)
Table 3 lists the AGP interface signals.
Table 3. AGP Signal Descriptions (Sheet 1 of 2)
Name
Type
Voltage
Description
GAD[31:0]
I/O
AGP
V_3
AGP Address/Data:
The standard AGP address and data lines.
This bus functions in the same way as the PCI AD[31:0] bus. The
address is driven with FRAME# assertion and data is driven or
received in following clocks.
GC/BE[3:0]#
I/O
AGP
V_3
AGP Command/Byte Enable:
This bus carries the command
information during AGP cycles when PIPE# is used. During an AGP
write, this bus contains byte enable information. The command is
driven with FRAME# assertion and byte enables corresponding to
supplied or requested data are driven on the following clocks.
GFRAME#
I/O
AGP
V_3
AGP Frame:
Not used during AGP transactions. Remains
deasserted by an internal pullup resistor. Assertion indicates the
address phase of a PCI transfer. Negation indicates that the cycle
initiator desires one more data transfer.
GDEVSEL#
I/O
AGP
V_3
AGP Device Select:
Same function as PCI DEVSEL#. It is not
used during AGP transactions. The 82443BX Host
Bridge/Controller drives this signal when a PCI initiator is attempting
to access DRAM. DEVSEL# is asserted at medium decode time.
GIRDY#
I/O
AGP
V_3
AGP Initiator Ready:
Indicates the AGP compliant target is ready
to provide allwrite data for the current transaction. Asserted when
the initiator is ready for a data transfer.
GTRDY#
I/O
AGP
V_3
AGP Target Ready:
Indicates the AGP compliant master is ready
to provide allwrite data for the current transaction. Asserted when
the target is ready for a data transfer.
GSTOP#
I/O
AGP
V_3
AGP Stop:
Same function as PCI STOP#. It is not used during AGP
transactions. Asserted by the target to request the master to stop
the current transaction.
GREQ#
I
AGP
V_3
AGP Request:
AGP master requests for AGP.
GGNT#
O
AGP
V_3
AGP Grant:
Same function as on PCI. Additional information is
provided on the ST[2:0] bus. PCI Grant: Permission is given to the
master to use PCI.
GPAR
I/O
AGP
V_3
AGP Parity:
A single parity bit is provided over GAD[31:0] and
GC/BE[3:0]. This signal is not used during AGP transactions.
PIPE#
I
AGP
V_3
Pipelined Request:
Asserted by the current master to indicate a
full width address that is to be queued by the target. The master
queues one request each rising clock edge while PIPE# is asserted.
SBA[7:0]
I
AGP
V_3
Sideband Address:
This bus provides an additional conduit to
pass address and commands to the 82443BX Host
Bridge/Controller from the AGP master.
RBF#
I
AGP
V_3
Read Buffer Full:
Indicates if the master is ready to accept
previously requested, low-priority read data.
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