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參數(shù)資料
| 型號： | Pentium II 333 |
| 廠商： | Intel Corp. |
| 英文描述： | Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器) |
| 中文描述： | 而對整個處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器） |
| 文件頁數(shù)： | 10/50頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | PENTIUM II 333 |
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Pentium
II
Processor with On-Die Cache – Low-Power Module
10
Datasheet
3.1.2
Memory (109 Signals)
Table 2 lists the memory interface signals.
Table 2. Memory Signal Descriptions
Name
Type
Voltage
Description
MECC[7:0]
I/O
CMOS
V_3
Memory ECC Data:
These signals carry Memory ECC data during
access to DRAM.
These pins are implemented by design but not tested on the
module.
RASA[5:0]# or
CSA[5:0]#
O
CMOS
V_3
Row Address Strobe (EDO):
These pins select the DRAM row.
Chip Select (SDRAM):
These pins activate the SDRAMs.
SDRAM
accepts any command when its CS# pin is active low.
CASA[7:0]# or
DQMA[7:0]
O
CMOS
V_3
Column Address Strobe (EDO):
These pins select the DRAM
column.
Input/Output Data Mask (SDRAM):
These pins act as
synchronized output enables during a read cycle and as a byte
mask during a write cycle.
MAB[9:0]#
MAB[10]
MAB[12:11]#
MAB[13]
O
CMOS
V_3
Memory Address (EDO/SDRAM):
This is the row and column
address for DRAM.
The 82443BX Host Bridge/Controller has two
identical sets of address lines (MAA and MAB#). The module
supports only the MAB set of address lines. For additional
addressing features, please refer to the Intel
440BX AGPset:
82443BX Host Bridge/Controller datasheet.
MWEA#
O
CMOS
V_3
Memory Write Enable (EDO/SDRAM):
MWEA# should be used as
the write enable for the memory data bus.
SRASA#
O
CMOS
V_3
SDRAM Row Address Strobe (SDRAM):
When active low, this
signal latches Row Address on the positive edge of the clock. This
signal also allows Row access and pre-charge.
SCASA#
O
CMOS
V_3
SDRAM Column Address Strobe (SDRAM):
When active low, this
signal latches Column Address on the positive edge of the clock.
This signal also allows Column access.
CKE[5:0]
O
CMOS
V_3
SDRAM Clock Enable (SDRAM):
SDRAM clock enable pin. When
these signals are deasserted, SDRAM enters power-down mode.
Each row is individually controlled by its own clock enable.
MD[63:0]
I/O
CMOS
V_3
Memory Data:
These signals are connected to the DRAM data bus.
They are not terminated on the module.
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