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參數(shù)資料
| 型號： | Pentium II 333 |
| 廠商： | Intel Corp. |
| 英文描述： | Processor with On-Die Cache Low-Power Module(帶片上緩存低能量模塊的處理器) |
| 中文描述： | 而對整個處理器模高速緩存低功率模塊（帶片上緩存低能量模塊的處理器） |
| 文件頁數(shù)： | 17/50頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | PENTIUM II 333 |
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Pentium
II
Processor with On-Die Cache – Low-Power Module
Datasheet
17
3.1.9
Voltages (54 Signals)
Table 9 lists the voltage signal definitions.
3.1.10
ITP/JTAG (9 Signals)
Table 10 lists the ITP/JTAG signals, which the system manufacturer can use to implement a JTAG
chain and an ITP port if desired.
Table 9. Voltage Descriptions
Name
Type
Number of
Pins
Description
V_DC
I
20
DC Input:
5 V-21 V
SUSB# controlled 3.3 V:
This rail is not used on the module. It is a
power managed 3.3 V supply.
An output of the voltage regulator on
the system electronics. This rail is off during STR, STD, and SOff.
SUSC# controlled 5 V:
Power managed 5 V supply.
An output of
the voltage regulator on the system electronics. This rail is off
during STD and SOff.
SUSC# controlled 3.3 V:
Power managed 3.3 V supply.
An output
of the voltage regulator on the system electronics. This rail is off
during STD and SOff.
AGP I/O Voltage
: This voltage rail is not implemented on module.
Intel recommends that this voltage rail be connected to V_3 on the
system electronics.
Processor I/O Ring:
Driven by the module to power processor
interface signals such as the PIIX4E open-drain pullups for the
processor/PIIX4E sideband signals.
Processor Clock Rail:
Driven by the module to power CK100-M
VDDCPU rail.
V_3S
I
9
V_5
I
3
V_3
I
16
VCCAGP
I
4
V_CPUPU
O
1
V_CLK
O
1
Table 10. ITP/JTAG Pins
Name
Type
Voltage
Description
TDO
O
V_CPUPU
JTAG Test Data Out:
Serial output port. TAP instructions and data
are shifted out of the processor from this port.
JTAG Test Data In:
Serial input port. TAP instructions and data are
shifted into the processor from this port.
JTAG Test Mode Select:
Controls the TAP controller change
sequence.
JTAG Test Clock:
Testability clock for clocking the JTAG boundary
scan sequence.
JTAG Test Reset:
Asynchronously resets the TAP controller in the
processor.
Processor Reset:
Processor reset status to the ITP.
GTL+ Termination Voltage:
Used by the POWERON pin on the
ITP debug port to determine when target system is on. POWERON
pin is pulled up using a 1-K
resistor to VTT.
Debug Mode Request:
Driven by the ITP and makes request to
enter debug mode.
Debug Mode Ready:
Driven by the processor and informs the ITP
that the processor is in debug mode.
TDI
I
V_CPUPU
TMS
I
V_CPUPU
TCLK
I
V_CPUPU
TRST#
I
V_CPUPU
FS_RESET#
O
GTL+
VTT
O
V_CORE
FS_PREQ#
I
V_CPUPU
FS_PRDY#
O
GTL+
NOTE:
DBREST# (reset target system) on the ITP debug port can be “l(fā)ogically ANDed” with VR_PWRGD TO
PIIX4E’s PWROK
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