![](http://datasheet.mmic.net.cn/180000/NT5TU64M16DG-3C_datasheet_11338978/NT5TU64M16DG-3C_75.png)
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
75
REV 1.0
06 / 2010
Slew rate Measurements
Output Slew rate
With the reference load for timing measurements output slew rate for falling and rising edges is measured between VTT -
250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS /
) output slew rate is measured
between DQS -
= - 500 mV and DQS - = + 500 mV. Output slew rate is guaranteed by design, but is not
necessarily tested on each device.
Input Slew rate - Differential signals
Input slew rate for differential signals (CK /
, DQS / , RDQS / ) for rising edges are measured from CK - =
-250 mV to CK -
= + 500 mV and from CK - CK = +250 mV to CK - CK = - 500mV for falling edges.
Input Slew rate - Single ended signals
Input slew rate for single ended signals (other than tis, tih, tds and tdh) are measured from dc-level to ac-level: VREF -125
mV to VREF + 250 mV for rising edges and from VREF + 125 mV to VREF - 250 mV for falling edges. For slew rate
definition of the input and data setup and hold parameters see section 8.3 of this datasheet.
Input and Data Setup and Hold Time
Timing Definition for Input Setup (tIS) and Hold Time (tIH)
Address and control input setup time (tIS) is referenced from the input signal crossing at the VIH(ac) level for a rising signal
and VIL(ac) for a falling signal applied to the device under test. Address and control input hold time (tIH) is referenced from
the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
t
IS
t
IH
t
IS
t
IH
CK