參數(shù)資料
型號(hào): NT5TU64M16DG-3C
廠商: NANYA TECHNOLOGY CORP
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝: GREEN, BGA-84
文件頁數(shù): 28/85頁
文件大小: 2622K
代理商: NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
34
REV 1.0
06 / 2010
Write Data Mask
One write data mask input (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, consistent with the
implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a
uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM of x4 and x16 bit
organization is not used during read cycles. However, DM of x8 bit organization can be used as RDQS during read cycles
by EMRS (1) setting.
Write Data Mask Timing
DQS
,
DQS
tDQSH
tDQSL
tWPRE
WPST
t
DQ
Din
tDS
DH
t
DM
don't care
Burst Write Operation with Data Mask: RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3, BL = 4
NOP
WRITE A
T0
T2
T1
T3
T4
T5
T6
T7
T9
WL = RL-1 = 2
DM
CMD
DQ
NOP
tWR
<= tDQSS
Precharge
Bank A
Activate
tRP
DQS,
DQS
DM
DIN A0 DIN A1
DIN A3
DIN A2
CK, CK
相關(guān)PDF資料
PDF描述
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
NTA2425-10
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