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參數(shù)資料
| 型號： | NT5TU64M16DG-3C |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封裝： | GREEN, BGA-84 |
| 文件頁數(shù)： | 19/85頁 |
| 文件大?。?/td> | 2622K |
| 代理商： | NT5TU64M16DG-3C |
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
26
REV 1.0
06 / 2010
Bank Activate Command
The Bank Activate command is issued by holding
and high plus and low at the rising edge of the clock.
The bank addresses BA0 ~ BA2 are used to select the desired bank. The row addresses A0 through A13 are used to
determine which row to activate in the selected bank for and x8 organized components. For x16 components row
addresses A0 through A12 have to be applied. The Bank Activate command must be applied before any Read or Write
operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write
command (with or without Auto-Precharge) on the following clock cycle. If an R/W command is issued to a bank that has
not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay the R/W command
which is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive
latencies of 0, 1, 2, 3, 4, 5, and 6 are supported. Once a bank has been activated it must be precharged before another
Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP,
respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined
(tRC). The minimum time interval between Bank Active commands, to other bank, is the Bank A to Bank B delay time (tRRD).
In order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices,
certain restrictions on operation of the 8 bank devices must be observed. There are two rules. One for restricting the
number of sequential ACTcommands that can be issued and another for allowing more time for RAS precharge for a
Precharge All command. The rules are list as follow:
* 8 bank device sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling tFAW window.
Conveting to clocks is done by dividing tFAW by tCK and rounding up to next integer value. As an example of the rolling
window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further
activate commands may be issued in clock N+1 through N+9.
*8 bank device Precharge All Allowance: tRP for a Precharge All command for an 8 Bank device will equal to tRP+tCK,
where tRP is the value for a single bank pre-charge.
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
Address
NOP
Command
T0
T2
T1
T3
T4
Col. Addr.
Bank A
Row Addr.
Bank B
Col. Addr.
Bank B
Internal RAS-CAS delay tRCDmin.
Bank A to Bank B delay tRRD.
Activate
Bank B
Read A
Posted CAS
Activate
Bank A
Read B
Posted CAS
Read A
Begins
Row Addr.
Bank A
Addr.
Bank A
Precharge
Bank A
NOP
Addr.
Bank B
Precharge
Bank B
Row Addr.
Bank A
Activate
Bank A
tRP Row Precharge Time (Bank A)
tRC Row Cycle Time (Bank A)
Tn
Tn+1
Tn+2
Tn+3
ACT
RAS-RAS delay tRRD.
tRAS Row Active Time (Bank A)
additive latency AL=2
CK, CK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5TU64M16GG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16GG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16HG-AC | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5TU64M16HG-BE | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT6 | 功能描述:烙鐵 Weller Chisel Tip For WMP Solder Penc RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included |
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