參數(shù)資料
型號: NT5TU64M16DG-3C
廠商: NANYA TECHNOLOGY CORP
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝: GREEN, BGA-84
文件頁數(shù): 55/85頁
文件大?。?/td> 2622K
代理商: NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
59
REV 1.0
06 / 2010
Output Buffer Levels
Output AC Test Conditions
Symbol
Parameter
SSTL-18 Class II
Units
Notes
VOTR
Output Timing Measurement Reference Level
0.5 * VDDQ
V
1
1. The VDDQ of the device under test is referenced.
Output DC Current Drive
Symbol
Parameter
SSTL-18
Units
Notes
IOH(dc)
Output Minimum Source DC Current, nominal
-13.4
mA
1, 3, 4
IOL(dc)
Output Minimum Sink DC Current, nominal
13.4
mA
2, 3, 4
1. VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT-VDDQ) / IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV.
2. VDDQ = 1.7 V;
VOUT =
280 mV. VOUT / IOL must be less than 21 ohm for values of VOUT between 0V and 280 mV.
3.
The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in note 1 and 2. They are used to test drive current capability to
ensure VIHmin. plus a noise margin and VILmax. minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are
derived by shifting the desired driver operating points along 21 ohm load line to define a convenient current for measurement.
OCD Default Setting Table
Symbol
Description
Min.
Nominal
Max.
Unit
Notes
-
Pull-up / Pull down mismatch
0
-
4
Ohms
6
-
Output Impedance step size for OCD calibration
0
-
1.5
Ohms
1,2,3
SOUT
Output Slew Rate
1.5
-
5
V / ns
1,4,5,7,8
1)
Absolute Specification: TOPEN; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V.
2)
Impedance measurement condition for output source dc current: VDDQ = 1.7V, VOUT = 1420 mV; (VOUT-VDDQ)/IOH must be less than
23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7
V; VOUT = -280mV; VOUT / IOL must be less than 23.4 ohms for values of VOUT between 0V and 280 mV.
3)
Mismatch is absolute value between pull-up and pull-down; both are measured at same temperature and voltage.
4)
Slew rates measured from VIL(AC) to VIH(AC) with the load specified in Section 8.2.
5) The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC.
This is guaranteed by design and characterization.
6) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only
the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 ohms under nominal
conditions.
7) DRAM output slew rate specification applies to 533MT/s, 667MT/s, and 800MT/s speed pin.
8) Timing skew due to DRAM output slew rate mis-match between DQS /
and associated DQ's is included in tDQSQ and tQHS
specification.
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NTA2425-10
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