參數(shù)資料
型號(hào): NT5TU64M16DG-3C
廠商: NANYA TECHNOLOGY CORP
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝: GREEN, BGA-84
文件頁(yè)數(shù): 14/85頁(yè)
文件大?。?/td> 2622K
代理商: NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
21
REV 1.0
06 / 2010
OCD impedance adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS (1) command along with a 4 bit burst code to
DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before
activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 is the table means all DQ bits at
bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs
simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength
setting. The maximum step count for adjustment can be up to 16 and when the limit is reached, further increment or
decrement code has no effect. The default setting may be any step within the maximum step count range. When Adjust
mode command is issued, AL from previously set value must be applied.
4 bit burst code inputs to all DQs
Operation
DT0
DT1
DT2
DT3
Pull-up driver strength
Pull-down driver strength
0
NOP (no operation)
0
1
Increase by 1 step
NOP
0
1
0
Decrease by 1 step
NOP
0
1
0
NOP
Increase by 1 step
1
0
NOP
Decrease by 1 step
0
1
0
1
Increase by 1 step
0
1
0
Decrease by 1 step
Increase by 1 step
1
0
1
Increase by 1 step
Decrease by 1 step
1
0
1
0
Decrease by 1 step
Other Combinations
Reserved
For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and tDS / tDH should be met as the following timing
diagram. Input data pattern for adjustment, DT0 ~ DT3 is fixed and not affected by MRS addressing mode (i.e. sequential or
interleave).
相關(guān)PDF資料
PDF描述
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
NTA2425-10
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