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參數(shù)資料
| 型號： | NT5TU64M16DG-3C |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封裝： | GREEN, BGA-84 |
| 文件頁數(shù)： | 20/85頁 |
| 文件大?。?/td> | 2622K |
| 代理商： | NT5TU64M16DG-3C |
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
27
REV 1.0
06 / 2010
Read and Write Commands and Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting
high, and
low at the clocks rising edge. must also be defined at this time to determine whether the access cycle is a read
operation (
high) or a write operation ( low). The DDR2 SDRAM provides a fast column access operation. A single
Read or Write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst
cycle is restricted to specific segments of the page length.
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of
BL=8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes
interrupted by a write with 4 bit burst boundary respectively, and the minimum
to delay (tCCD) is minimum 2
clocks for read or write cycles.
Posted
Posted
operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2
SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the
bank activate command (or any time during the
to delay time, tRCD, period). The command is held for the time of
the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and the
latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin, then AL greater than 0
must be written into the EMRS (1). The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read
Latency is defined as the sum of Additive Latency plus
latency (RL=AL+CL). If a user chooses to issue a Read
command after the tRCDmin period, the Read Latency is also defined as RL = AL + CL.
Example of posted
operation:
Read followed by a write to the same bank:
AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
Dout0 Dout1 Dout2Dout3
CMD
DQ
0
2
3
4
5
6
7
8
9
10
11
12
-1
1
>=tRCD
AL = 2
RL = AL + CL = 5
CL = 3
WL = RL -1 = 4
Din0 Din1
Din2 Din3
PostCAS1
DQS,
DQS
Activate
Read
Write
Bank A
CK, CK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5TU64M16GG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16GG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16HG-AC | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5TU64M16HG-BE | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT6 | 功能描述:烙鐵 Weller Chisel Tip For WMP Solder Penc RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included |
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