![](http://datasheet.mmic.net.cn/180000/NT5TU64M16DG-3C_datasheet_11338978/NT5TU64M16DG-3C_57.png)
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
57
REV 1.0
06 / 2010
DC & AC Logic Input Levels
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the
EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by
which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are
measured relative to the rising or falling edges of DQS crossing at VREF.
In differential mode, these timing relationships
are measured relative to the cross point of DQS and its complement, DQS. This distinction in timing methods is guaranteed
by design and characterization
. In single ended mode, the DQS (and RDQS) signals are internally disabled and dont care.
Single-ended DC & AC Logic Input Levels
Symbol
Parameter
DDR2-667/800
Units
Min.
Max.
VIH (dc)
DC input logic high
VREF + 0.125
VDDQ + 0.3
V
VIL (dc)
DC input low
-0.3
VREF - 0.125
V
VIH (ac)
AC input logic high
VREF + 0.200
VDDQ+Vpeak
V
VIL (ac)
AC input low
VSSQ-Vpeak
VREF - 0.200
V
Single-ended AC Input Test Conditions
Symbol
Condition
Value
Units
Notes
VREF
Input reference voltage
0.5 * VDDQ
V
1, 2
VSWING(max)
Input signal maximum peak to peak swing
1
V
1, 2
SLEW
Input signal minimum slew rate
1
V / ns
3, 4
1. This timing and slew rate definition is valid for all single-ended signals except tis, tih, tds, tdh.
2. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
3. The input signal minimum slew rate is to be maintained over the range from VIL(dc)max to VIH(ac)min for rising edges and the range from VIH(dc)min to VIL(ac)max for falling
edges as shown in the below figure.
4. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions.