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參數(shù)資料
| 型號(hào)： | NT5TU64M16DG-3C |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封裝： | GREEN, BGA-84 |
| 文件頁數(shù)： | 27/85頁 |
| 文件大?。?/td> | 2622K |
| 代理商： | NT5TU64M16DG-3C |
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
33
REV 1.0
06 / 2010
Burst Write Operation: RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4
NOP
WRITE A
Post CAS
T0
T2
T1
T3
T4
T5
T6
T7
T9
WL = RL-1 = 2
BW322
CMD
DQ
NOP
DIN A0 DIN A1 DIN A2 DIN A3
tWR
Completion of
the Burst Write
<= tDQSS
Precharge
Bank A
Activate
tRP
DQS,
DQS
CK, CK
Burst Write followed by Burst Read: RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4
NOP
READ A
Post CAS
BWBR
CMD
DQ
NOP
DIN A0 DIN A1 DIN A2 DIN A3
AL=2
CL=3
NOP
tWTR
T0
T2
T1
T3
T4
T5
T6
T7
T8
T9
Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6
DQS,
DQS
WL = RL - 1 = 4
RL=5
CK, CK
The minimum number of clocks from the burst write command to the burst read command is (CL - 1) +BL/2 +
tWTR where
tWTR is the write-to-read
turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery time (tWR) but the
time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.
Seamless Burst Write Operation: RL = 5, WL = 4, BL = 4
NOP
DIN A0 DIN A1 DIN A2 DIN A3
WRITE A
Post CAS
WL = RL - 1 = 4
WRITE B
Post CAS
DIN B0 DIN B1 DIN B2 DIN B3
T0
T2
T1
T3
T4
T5
T6
T7
T8
CMD
DQ
SBR
DQS,
DQS
CK, CK
The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5TU64M16GG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16GG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16HG-AC | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5TU64M16HG-BE | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
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