![](http://datasheet.mmic.net.cn/180000/NT5TU64M16DG-3C_datasheet_11338978/NT5TU64M16DG-3C_18.png)
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
18
REV 1.0
06 / 2010
EMRS(2) Extended Mode Register Set Programming
Address Field
Extended Mode
Register
1
PASR***
BA1 BA0
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0*
A2
A1
A0
Partial Array Self Refresh
0
Full array
0
1
Half Array (BA[2:0]=000, 001, 010, &011)
0
1
0
Quarter Array (BA[2:0]=000&001)
0
1
1/8
th array (BA[2:0] = 000)
1
0
3 / 4 array (BA[2:0]=010,011,100,101,110, &111)
1
0
1
Half array (BA[2:0]=100, 101, 110, & 111)
1
0
Quarter array (BA[2:0]=110&111)
1
1/8
th array (BA[2:0]=111)
0
SRF
A7
0
Disable
1
Enable** (85C Tcase 95C)
High Temperature Self-Refresh Rate Enable
A12
0*
BA2
0*
BA0
MRS mode
0
MRS
1
EMRS(1)
BA1
0
1
0
EMRS(2)
EMRS(3):
Reserved
* The rest bits in EMRS(2) is reserved for future use and all bits in EMRS (2) except A0-A2,A7,BA0, and
BA1 must be programmed to 0 when setting EMRS (2) during initialization.
** DDR2 SDRAM Module user can look at module SPD field Byte 49 bit [0].
*** Optional. If PASR(Partial Array Self Refresh ) is enabled, data located in areas of the array beyond the
spec. location will be lost if self refresh is entered .
Extended Mode Register Set EMRS (2)
The Extended Mode Registers (2) controls refresh related features. The default value of the extended mode register(2) is
not defined, therefore the extended mode register(2) is written by asserting low on CS, RAS, CAS, WE, BA0, high on BA1,
while controlling the states of address pin A0-A13. The DDR2 SDRAM should be in all bank precharge with CKE already
high prior to writing into the extended mode register (2). The mode register set command cycle time (tMRD) must be
satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using
the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state.
EMRS(3) Extended Mode Register Set Programming
All bits in EMRS(3) expect BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the mode
register during initialization.