參數資料
型號: NT5TU64M16DG-3C
廠商: NANYA TECHNOLOGY CORP
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝: GREEN, BGA-84
文件頁數: 31/85頁
文件大?。?/td> 2622K
代理商: NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
37
REV 1.0
06 / 2010
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge
Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The
Pre-charge Command can be used to precharge each bank independently or all banks simultaneously. Three
address bits A10, BA0, BA1, and BA2 are used to define which bank to precharge when the command is
issued.
Bank Selection for Precharge by Address Bit
A10
BA2
BA1
BA0
Precharge
Bank(s)
LOW
Bank 0 only
LOW
HIGH
Bank 1 only
LOW
HIGH
LOW
Bank 2 only
LOW
HIGH
Bank 3 only
LOW
HIGH
LOW
Bank 4 only
LOW
HIGH
LOW
HIGH
Bank 5 only
LOW
HIGH
LOW
Bank 6 only
LOW
HIGH
Bank 7 only
HIGH
Don't Care
all banks
Burst Read Operation Followed by a Precharge
Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max (RTP, 2) - 2 clocks.
For the earliest possible precharge, the Precharge command may be issued on the rising edge which is “Additive Latency
(AL) + BL/2
clocks” after a Read Command, as long as the minimum tRAS timing is satisfied.
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates
the last 4-bit prefetch of a Read to Precharge command. This time is call tRTP (Read to Precharge). For BL=4 this is the
time from the actual read (AL after the Read command) to Precharge command. For BL=8 this is the time from AL + 2
clocks after the Read to the Precharge command.
相關PDF資料
PDF描述
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
NTA2425-10
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