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參數(shù)資料
| 型號(hào)： | NT5TU64M16DG-3C |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封裝： | GREEN, BGA-84 |
| 文件頁數(shù)： | 6/85頁 |
| 文件大?。?/td> | 2622K |
| 代理商： | NT5TU64M16DG-3C |
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
14
REV 1.0
06 / 2010
Register Definition
Programming the Mode Registration and Extended Mode Registers
For application flexibility, burst length, burst type,
latency, DLL reset function, write recovery time (tWR) are user
defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable
function, additive
latency, driver impedance, ODT (On Die Termination), single-ended strobe and OCD (off chip
driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register
Set (EMRS) command. Contents of the Mode Register (MR) and Extended Mode Registers (EMR (#)) can be altered by
re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables,
all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and DLL Reset do not affect
array contents, which mean re-initialization including those can be executed any time after power-up without affecting
array contents.
Mode Registration Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls
latency,
burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM
useful for various applications. The default value of the mode register is not defined, therefore the mode register must be
written after power-up for proper operation. The mode register is written by asserting low on
, , , , BA0 and
BA1, while controlling the state of address pins A0 ~ A13. The DDR2 SDRAM should be in all banks precharged (idle)
mode with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is
required to complete the write operation to the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during normal operation as long as all banks are in the precharged state.
The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options
of 4 and 8 bit burst length. Burst address sequence type is defined by A3 and
latency is defined by A4 ~ A6. A7 is
used for test mode and must be set to low for normal MRS operation. A8 is used for DLL reset. A9 ~ A11 are used for
write recovery time (WR) definition for Auto-Precharge mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5TU64M16GG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16GG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16HG-AC | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5TU64M16HG-BE | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT6 | 功能描述:烙鐵 Weller Chisel Tip For WMP Solder Penc RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included |
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