![](http://datasheet.mmic.net.cn/180000/NT5TU64M16DG-3C_datasheet_11338978/NT5TU64M16DG-3C_11.png)
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
11
REV 1.0
06 / 2010
Block Diagram (64Mb x 16)
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
I/O Gating
DM Mask Logic
Bank 7
Row-Address
Latch &
Decoder
Bank 6
Row-Address
Latch &
Decoder
Bank 5
Row-Address
Latch &
Decoder
Bank 4
Row-Address
Latch &
Decoder
Bank 3
Row-Address
Latch &
Decoder
Bank 2
Row-Address
Latch &
Decoder
Bank 1
Row-Address
Latch &
Decoder
Command
Decode
Mode
Registers
Control Logic
CKE
CK
CS
WE
CAS
RAS
A
dd
re
ss
R
eg
ist
er
16
R
ow
-A
dd
re
ss
M
U
X
13
A0 – A12,
BA0 – BA2
10
16
13
R
ef
re
sh
C
ou
nte
r
Column-Address
Counter/Latch
3
Bank Control
Logic
8
Bank 0
Row-Address
Latch &
Decoder
Bank 7
Memory Array
(16384 x512 x16)
Sense Amplifier
Bank 6
Memory Array
(16384 x512 x16)
Sense Amplifier
Bank 5
Memory Array
(16384 x512 x16)
Sense Amplifier
Bank 4
Memory Array
(16384 x512 x16)
Sense Amplifier
Bank 3
Memory Array
(16384 x512 x16)
Sense Amplifier
Bank 2
Memory Array
(16384 x512 x16)
Sense Amplifier
Bank 1
Memory Array
(16384 x512 x16)
Sense Amplifier
Bank 0
Memory Array
(8192 x 256 x 64)
Sense Amplifier
8192
16384
256 (x64)
8
2
64
R
ea
d
L
atc
h
Write
FIFO
&
Drivers
16
MUX
COL0,1
D
riv
er
s
DQS
Generator
16
4
Data
UDQS,
LDQS,
2
16
2
16
8
Mask
64
Data
COL0,1
CK,
CK
2
16
R
ec
eiv
er
s
O
D
T
C
on
tro
l
UDM,
LDM
UDQS,
UDQS
DQ0 –
DQ15
ODT
DLL
CK, CK
13
3
COL0,1
Input
Register
Notes:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DM is an unidirectional signal (input only), but it is internally loaded to match the load of the bidirectional DQ
and DQS signals.
LDQS,
LDQS
4