參數(shù)資料
型號(hào): NT5TU64M16DG-3C
廠商: NANYA TECHNOLOGY CORP
元件分類(lèi): DRAM
英文描述: 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝: GREEN, BGA-84
文件頁(yè)數(shù): 39/85頁(yè)
文件大?。?/td> 2622K
代理商: NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
44
REV 1.0
06 / 2010
Burst Write with Auto-Precharge
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM
automatically begins precharge operation after the completion of the write burst
plus the
write recovery time delay (WR),
programmed
in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Precharge from the completion of
the write burst may be reactivated if the following two conditions are satisfied.
(1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Examples:
Burst Write with Auto-Precharge (tRC Limit): WL = 2, tDAL = 6 (WR = 3, tRP = 3), BL = 4
NOP
Bank A
Activate
NOP
WRITE
w/AP
T0
T2
T1
T3
T4
T5
T6
T7
NOP
CMD
DQ
BW-AP223
A10 ="high"
tRP
Auto-Precharge Begins
DIN A0 DIN A1 DIN A2 DIN A3
WL = RL-1 = 2
WR
tRCmin.
DQS,
DQS
Completion of the Burst Write
tDAL
>=tRASmin.
CK, CK
Burst Write with Auto-Precharge (tWR + tRP Limit) : WL = 4, tDAL = 6 (tWR = 3, tRP = 3), BL = 4
NOP
Bank A
Activate
NOP
Posted CAS
WRITE w/AP
T
0
T
3
T
4
T
5
T
6
T
7
T12
NOP
CMD
DQ
BW-AP423
A10 ="high"
tRP
Auto-Precharge Begins
DIN
A0
DIN
A1
DIN
A2
DIN
A3
WL = RL-1 = 4
tWR
>=tRC
T
9
T
8
Completion of the Burst Write
DQS,
DQS
tDAL
>=tRAS
CK, CK
相關(guān)PDF資料
PDF描述
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
NTA2425-10
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