參數(shù)資料
型號(hào): NT5TU64M16DG-3C
廠商: NANYA TECHNOLOGY CORP
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝: GREEN, BGA-84
文件頁(yè)數(shù): 17/85頁(yè)
文件大小: 2622K
代理商: NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
24
REV 1.0
06 / 2010
ODT related timings
MRS command to ODT update delay
During normal operation the value of the effective termination resistance can be changed with an EMRS command. The
update of the Rtt setting is done between tMOD, min and tMOD, max, and CKE must remain HIGH for the entire duration of
tMOD window for proper operation. The timings are shown in the following timing diagram.
CKE
Rtt
CK, CK
tIS
CMD
tAOFD
EMRS
NOP
tMOD, min
tMOD, max
Old setting
Updating
New setting
EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal)
Setting in this diagram is the Register and I/O setting, not what is measured from outside.
However, to prevent any impedance glitch on the channel, the following conditions must be met.
- tAOFD must be met before issuing the EMRS command.
- ODT must remain LOW for the entire duration of tMOD window, until tMOD, max is met.
Now the ODT is ready for normal operation with the new setting, and the ODT may be raised again to turn on the ODT.
Following timing diagram shows the proper Rtt update procedure.
CKE
Rtt
CK, CK
tIS
CMD
tAOFD
EMRS
NOP
tMOD, max
Old setting
New setting
EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal)
Setting in this diagram is the Register and I/O setting, not what is measured from outside.
tAOND
NOP
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PDF描述
NTA2425E
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NTA2410-10
NTD2410F
NTA2425-10
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