參數(shù)資料
型號(hào)： NS32FX100VF
廠商： National Semiconductor Corporation
英文描述： System Controller
中文描述： 系統(tǒng)控制器
文件頁(yè)數(shù)： 77/94頁(yè)
文件大小： 955K
代理商： NS32FX100VF
4.0 Device Specifications
(Continued)
4.6.2 Timing Tables
(Continued)
4.6.2.2 Input Signal Requirements
(Continued)
Symbol
Figure
Description
Reference/
Condition
NS32FX200-15
NS32FX200-20
NS32FX200-25
Units
Min
Max
Min
Max
Min
Max
t
ADSs
4-9
ADS Signal
Setup
Before R.E.,
CTTL T2
51
36
27
ns
t
ADSw
4-9
ADS Pulse
Width
At 0.8V
(Both Edges)
20
15
10
ns
t
Ds
4-16
Data Setup
Before R.E.,
CTTL T4
15
14
10
ns
t
Dh
4-16
Data Hold
After R.E.,
CTTL T4
0
0
0
ns
t
HBEs
4-9
HBE Signal
Setup
Before R.E.,
CTTL T2
51
36
27
ns
t
HBEh
4-9
HBE Signal
Hold
After R.E.,
CTTL next T1/i
0
0
0
ns
t
DDINs
4-9
DDIN Signal
Setup
Before R.E.,
CTTL T2
51
36
27
ns
t
DDINh
4-9
DDIN Signal
Hold
After R.E.,
CTTL next T1/i
0
0
0
ns
t
HLDAs
4-16
HLDA Signal
Setup
Before R.E.,
CTTL Ti
51
36
27
ns
t
HLDAh
4-16
HLDA Signal
Hold
After R.E.,
CTTL Ti
0
0
0
ns
t
SDINs
4-19
SDIN Signal
Setup
Before F.E.,
CTTL
15
14
12
ns
t
SDINh
4-19
SDIN Signal
Hold
After F.E.,
CTTL
0
0
0
ns
t
SVIs
4-27
SVI Signal Setup
(Notes 1, 2)
After L.E.,
SNH
t
SCMPRW
b
200 ns
t
SCMPRW
b
200 ns
t
SCMPRW
b
200 ns
ns
t
SVIh
4-27
SVI Signal
Hold
After L.E.,
Next SNH
0
0
0
ns
t
SBGs
4-27
SBG Signal Setup
(Notes 1, 2)
After L.E.,
SNH
t
SCMPRW
b
200 ns
t
SCMPRW
b
200 ns
t
SCMPRW
b
200 ns
ns
t
SBGh
4-27
SBG Signal
Hold
After L.E.,
Next SNH
0
0
0
ns
t
PFAILs
4-22
PFAIL Signal
Setup
Before R.E.,
CTTL
15
14
13
ns
t
PFAILh
4-22
PFAIL Signal
Hold
After R.E.,
CTTL
0
0
0
ns
t
INTs
4-18
INT0–3 Signal
Setup
Before R.E.,
CTTL
15
14
13
ns
t
INTh
4-18
INT0–3 Signal
Hold
After R.E.,
CTTL
0
0
0
ns
Note 1:
t
SCMPRW
e
(SCMPRW
a
1)
*
t
CTp
while SCMPRW is the programmed value in SCMPRW register. The current tolerance is 8
m
A.
Note 2:
The internal analog reset width, as programmed in the SCMPRW register, should be more than 200 ns. The analog reset should be terminated at least 300
ns before the next SNH leading edge.
77
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