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參數(shù)資料
| 型號： | NS32FX100VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | System Controller |
| 中文描述： | 系統(tǒng)控制器 |
| 文件頁數(shù)： | 18/94頁 |
| 文件大小： | 955K |
| 代理商： | NS32FX100VF |
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2.0 Architecture
(Continued)
SDTGC Transmit Gain Control register. Used to attenuate
the transmit IIR input samples. The value to be
written in SDTGC register is 16384
c
10
(Gain/20)
,
rounded to the nearest integer number.
Some examples are given in the following table:
Gain (dB)
SDTGC
b
42
b
41.9
0x0082
0x0084
.
.
0x4000
.
.
0
SDSTAT Status Register. Provides information about the
status of the Sigma-Delta operation.
7
6
5
4
3
2
1
0
TSAT
RSAT
TFNE
RFNE
TERR
RERR
TIRQ
RIRQ
RIRQ When ‘‘1’’ during receive enable (SDCNTL.RE
e
1),
it indicates that N or more samples are ready in the
receive FIFO. This bit will remain high as long as the
number of samples is greater than, or equal to, N. If
this bit is not masked by SDMASK.RIRQ it will cause
an interrupt.
When ‘‘1’’ during transmit enable (SDCNTL.TE
e
1),
it indicates that less than N samples are ready in the
transmit FIFO. This bit will remain high as long as
the number of samples is less than N. If this bit is not
masked by SDMASK.TIRQ it will cause an interrupt.
RERR When ‘‘1’’ during receive enable (SDCNTL.RE
e
1) it
indicates an attempt to read an empty receive FIFO,
or incoming sample when the receive FIFO is full. If
this bit is not masked by SDMASK.RERR it will
cause an interrupt.
TERR When ‘‘1’’ during transmit enable (SDCNTL.TE
e
1)
it indicates an attempt to read from an empty trans-
mit FIFO, or writing to a full transmit FIFO. If this bit
is not masked by SDMASK.TERR it will cause an
interrupt.
TIRQ
TFNE Transmit FIFO Not Empty, when ‘‘0’’ indicates that
the transmit FIFO is empty.
RFNE Receive FIFO Not Empty, when ‘‘0’’ indicates that
the receive FIFO empty.
RSAT Reception Saturation. This bit is set to ‘‘1’’, whenev-
er a saturation value is created in the receive IIR
(including the echo-canceling filter, when enabled)
or in the receive gain control logic.
TSAT Transmit Saturation. This bit is set to ‘‘1’’, whenever
a saturation value is created in the transmission IIR
or in DSDM.
Upon reset all implemented bits in the SDSTAT reg-
ister are cleared to ‘‘0’’.
SDMASK Mask Register. Enables masking of SDC inter-
rupts.
7
4
3
2
1
0
res
TERR
RERR
TIRQ
RIRQ
RIRQ
Mask Receive Interrupt Request.
0 : SDSTAT.RIRQ will not cause an interrupt.
1 : SDSTAT.RIRQ will cause an interrupt.
TIRQ
Mask Transmit Interrupt Request.
0 : SDSTAT.TIRQ will not cause an interrupt.
1 : SDSTAT.TIRQ will cause an interrupt.
RERR Mask Receive Error.
0 : SDSTAT.RER will not cause an interrupt.
1 : SDSTAT.RER will cause an interrupt.
TERR Mask Transmit Error.
0 : SDSTAT.TER will not cause an interrupt.
1 : SDSTAT.TER will cause an interrupt.
2.3.6 Usage Recommendations
The SDC should be enabled (by setting the SDC bit in the
MCFG register to ‘‘1’’) before programming SDMASK and
SDCNTL.
2.4 SCANNER CONTROLLER (SCANC)
2.4.1 Features
#
Programmable generation of control signals which sup-
port a wide range of Charge Coupled Device (CCD) and
Contact Image Sensor (CIS) scanners
#
Supports line scan times of 2.5 ms, 5 ms, 10 ms and
20 ms
#
On-Chip shading-correction circuitry, using reference line
values stored in the system RAM, via DMA channel 0
#
On-Chip dithering and Gamma correction circuit of 16
grey levels. (64 grey levels in NS32FX200)
#
Support for Automatic Background Control (ABC) and
edge enhancement with external circuitry
#
On-Chip multiplying Digital-to-Analog Converter (DAC)
for compensation of scanner offset
#
Automatic writing of scanned bitmap to memory via DMA
channel 2
#
Optional bypass of on-chip video-data generation to sup-
port external image enhancement
2.4.2 Operation
The Scanner Controller Module (SCANC) consists of a
scanner signals generator block, a video handling block
(shading compensation, dithering and bitmap accumulation)
and a stepper motor control block. The module includes
analog and digital circuits. It uses two DMA channelsDone
for fetching a reference line and one for storing the digitized
video data. The module is synchronized with the TCU mod-
ule. The operation of SCANC, and the allocation of DMA
channels 0 and 2 to the Scanner Controller or for external
usage, are controlled by the Module Configuration Register
(MCFG). The module’s minimum operation frequency is
14.7456 MHz (i.e., it can not operate in Power Save mode).
Some of the Scanner signals can be assigned to an I/O port
when the Scanner is not used (e.g., after reset).
18
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