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參數(shù)資料
| 型號(hào)： | NS32FX100VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | System Controller |
| 中文描述： | 系統(tǒng)控制器 |
| 文件頁數(shù)： | 41/94頁 |
| 文件大?。?/td> | 955K |
| 代理商： | NS32FX100VF |
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2.0 Architecture
(Continued)
2.9.3 Registers
IVCT:
Interrupt Vector register. Read only. 8-bit regis-
ter.
7
6
5
4
3
0
0
0
1
0
INTVECT
INTVECT: When INTR pin is active, this field contains the
encoded value of the enabled pending interrupt
that has the highest priority.
IENAM:
Interrupt Enable And Mask register. 16-bit regis-
ter.
Enables each interrupt individually.
The bits of IENAM correspond to interrupts 0–
15. Each bit is encoded as follows:
0 : Interrupt is disabled.
1 : Interrupt is enabled.
IPEND:
Interrupt Pending register. Read only. 16-bit reg-
ister.
Indicates which interrupts are pending. Bits 0–
15 of IPND correspond to interrupts 0–15. Each
bit is encoded as follows:
0 : Interrupt is not pending.
1 : Interrupt is pending.
IECLR:
Edge Interrupt Clear register. Write only. 16-bit
register.
Used to clear pending, edge-triggered, inter-
rupts. Writing to the bit positions of level-trig-
gered interrupts has no effect. The bits of IECLR
correspond to interrupts 0–15. Each bit is en-
coded as follows:
0 : No effect.
1 : Clear the pending interrupt.
IELTG:
Edge/Level Trigger. 16-bit register.
Each bit defines the way that the corresponding
interrupt request is triggered, either edge-sensi-
tive or level-sensitive.
Each IETLG bit is encoded as follows:
0 : Level-sensitive.
1 : Edge-sensitive.
For normal invocation of internal interrupt sourc-
es, bits 0, 5, 6, 7 and 8 must be ‘‘0’’; bits 2, 3, 10,
11, 12, 13 and 14 must be ‘‘1’’.
ITRPL:
Trigger Polarity. ITRPL is a 16-bit register that
controls the triggering polarity. ITRPL bits are
encoded as follows:
Level-sensitive trigger type:
0 : Low level.
1 : High level.
Edge-sensitive trigger type:
0 : Falling edge.
1 : Rising edge.
For normal invocation of internal interrupt sourc-
es, bits 0, 2, 3, 5, 6, 7, 8, 10, 11, 12, 13 and 14
must be ‘‘1’’.
Program the IELTG and ITRPL registers, to con-
trol the ICU mode and polarity, as follows:
IELTG
ITRPL
Mode
0
0
1
1
0
1
0
1
Low Level
High Level
Falling Edge
Rising Edge
2.9.4 Usage Recommendations
1. Initialization:
The recommended initialization sequence is:
a. Initialize the INTBASE register of the CPU
b. Program the interrupts’ triggering mode and polarity
c. Prepare the interrupt routines of the used interrupts
d. Clear the used edge-interrupt
e. Set the relevant bits of IENAM
f. Enable the CPU interrupt (via the PSR register of the
CPU)
2. Clearing:
Clearing an interrupt request before it is serviced may
cause a spurious interrupt, (i.e., the CPU detects an inter-
rupt not reflected by IVCT). The user is advised to clear
interrupt requests only when interrupts are disabled.
Changing triggering mode or polarity may also cause a
spurious interrupt and should thus be carried out only
when the interrupts are disabled.
Clearing any of the IENAM bits should be carried out
while the I bit in the PSR register of the CPU is cleared.
3. Nesting:
There is no hardware limitation on nesting of interrupts.
Interrupts’ nesting is controlled by writing into the Enable
And Mask register (IENAM). When the CPU acknowledg-
es an interrupt, the CPU’s PSR.I bit is cleared to ‘‘0’’,
thus disabling interrupts. While an interrupt is in service,
the user may allow other interrupts to occur by updating
IENAM, then setting PSR.I bit to ‘‘1’’. The IENAM register
can be used to control which of the other interrupts is
enabled.
2.10 PORTS MODULE
2.10.1 Features
Y
Individual or group enable/set/clear of any output port
Y
Read latched state of input ports
Y
Some Port I/O pins can be allocated to other modules
Y
External extension output port support
2.10.2 Operation
This module includes three types of ports:
D General-purpose input/output ports.
D External output port extension.
D Stepper-motors output ports.
2.10.2.1 General Purpose Input/Output Ports
These ports enable access to individual, general-purpose,
input/output pins. There are three general purpose ports.
Port A provides four input pins, Port B provides 12 output
pins, Port C provides eight I/O pins. Some pins are shared
41
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