參數(shù)資料
型號(hào)： NS32FX100VF
廠(chǎng)商： National Semiconductor Corporation
英文描述： System Controller
中文描述： 系統(tǒng)控制器
文件頁(yè)數(shù)： 75/94頁(yè)
文件大?。?/td> 955K
代理商： NS32FX100VF
4.0 Device Specifications
(Continued)
4.6.2 Timing Tables
(Continued)
4.6.2.1 Output Signals: Internal Propagation Delays
(Continued)
Symbol
Figure
Description
Reference/
Condition
NS32FX200-15
NS32FX200-20
NS32FX200-25
Units
Min
Max
Min
Max
Min
Max
t
UTXDa
4-24
UTXD Signal
Active
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
UTXDia
4-24
UTXD Signal
Inactive
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
URENa
4-24
UREN Signal
Active
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
URENia
4-24
UREN Signal
Inactive
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
MWSOa
4-25
MWSO Signal
Active (Note 1)
After R.E.,
CTTL
24
22
20
ns
t
MWSOia
4-25
MWSO Signal
Inactive (Note 1)
After R.E.,
CTTL
24
22
20
ns
t
PIOa
4-26
PIO0–1 Signal
Active
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
PIOia
4-26
PIO0–1 Signal
Inactive
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
SNHa
4-23
SNH Signal
Active
After R.E.,
CTTL
24
22
20
ns
t
SNHia
4-23
SNH Signal
Inactive
After R.E.,
CTTL
24
22
20
ns
t
SBYPSa
4-23
SBYPS Signal
Active
After R.E.,
CTTL
24
22
20
ns
t
SBYPSia
4-23
SBYPS Signal
Inactive
After R.E.,
CTTL
24
22
20
ns
t
ALf
4-17
AD0–AD15 Floating
(Note 4)
After R.E.,
CTTL Ti
15
14
13
ns
t
AHf
4-17
A16–A23 Floating
(Notes 3, 4)
After R.E.,
CTTL Ti
t
CTp/2
t
CTp/2
t
CTp/2
ns
t
ADSf
4-17
ADS Signal Floating
(Notes 3, 4)
After R.E.,
CTTL Ti
t
CTp/2
t
CTp/2
t
CTp/2
ns
t
DDINf
4-17
DDIN Signal
Floating (Notes 3, 4)
After R.E.,
CTTL Ti
t
CTp/2
t
CTp/2
t
CTp/2
ns
t
PCf
4-26
All Port B, C Outputs
Floating (Notes 2, 4)
After R.E.,
CTTL
0
t
CTp/2
a
15
0
t
CTp/2
a
14
0
t
CTp/2
a
13
ns
Note 1:
When configured as MWIRE signal, MWSO is changed on the first CTTL R.E. following the relevant MWSK edge.
Note 2:
SNH, PCLK, UTXD, UREN, MWSO, PIO0–1, SBYPS.
Note 3:
Float according to HLDA input.
Note 4:
The parameters related to the ‘‘floating/not floating’’ conditions are guaranteed by characterization. Due to tester conditions, these parameters are not
100% tested.
75
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