參數(shù)資料
型號(hào)： NS32FX100VF
廠(chǎng)商： National Semiconductor Corporation
英文描述： System Controller
中文描述： 系統(tǒng)控制器
文件頁(yè)數(shù)： 71/94頁(yè)
文件大?。?/td> 955K
代理商： NS32FX100VF
4.0 Device Specifications
(Continued)
4.6.2 Timing Tables
4.6.2.1 Output Signals: Internal Propagation Delays
Symbol
Figure
Description
Reference/
Condition
NS32FX200–15
NS32FX200–20
NS32FX200-25
Units
Min
Max
Min
Max
Min
Max
t
CLKp
4-8
CCLK Clock Period
R.E. CCLK to
next R.E. CCLK
33
500
25
500
20
500
ns
t
CLKh
4-8
CCLK High Time
At 3.8V
(Both Edges)
t
CLKp/2
b
5 ns
t
CLKP/2
b
4 ns
t
CLKp/2
b
3 ns
t
CLKl
4-8
CCLK Low Time
At 1.0V
(Both Edges)
t
CLKp/2
b
5 ns
t
CLKP/2
b
4 ns
t
CLKp/2
b
3 ns
t
CWa
4-9
CWAIT Signal Active
After R.E.,
CTTL
40
30
24
ns
t
CWia
4-9
CWAIT Signal
Inactive
After R.E.,
CTTL
40
30
24
ns
t
ADSOa
4-16
ADS Signal Active
(Notes 2, 5)
After R.E.,
CTTL
t
CTp/2
a
3
t
CTp/2
a
27
t
CTp/2
a
3
t
CTp/2
a
25
t
CT p/2
a
3
t
CTp/2
a
23
ns
t
ADSOia
4-16
ADS Signal
Inactive
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
27
t
CTp/2
t
CTp/2
a
25
t
CT p/2
t
CTp/2
a
23
ns
t
DDINv
4-16
DDIN Signal
Valid
Before F.E.,
CTTL T1
17
16
12
ns
t
DDINh
4-16
DDIN Signal
Hold
After F.E.,
CTTL T4
0
0
0
ns
t
HOLDa
4-16
HOLD Signal
Active
After R.E.,
CTTL
23
21
18
ns
t
HOLDia
4-16
HOLD Signal
Inactive
After R.E.,
CTTL
23
21
18
ns
t
MAv
4-9
MA1–15 Valid
(Note 3)
After R.E.,
CTTL T1
50
36
34
ns
t
MACv
4-9
MA1–15 Valid
Column Address
After R.E.,
CTTL T2
60
45
40
ns
t
MAh
4-9
MA1–15 Hold
After R.E.,
CTTL T2 or T4
t
CTp/2
a
0 ns
t
CTp/2
a
0 ns
t
CTp/2
a
0 ns
ns
t
RAh
4-9
MA1–15 Hold
(Notes 4, 5)
After F.E.,
RAS
25
18
14
ns
t
ADv
4-17
AD0–15 Valid
(Data) (Note 1)
After R.E.,
CTTL T2
t
CTp/2
t
CTp/2
a
25
t
CTp/2
t
CTp/2
a
20
t
CTp/2
t
CTp/2
a
20
ns
t
ADs
4-17
AD0–15 Setup
(Data) (Note 5)
Before R.E.,
WE0–1
40
30
18
ns
t
ADh
4-17
AD0–15 Hold
(Data)
After R.E.,
CTTL T4
t
CTP/2
t
CTP/2
t
CTP/2
ns
Note 1:
t
CASa
–t
ADv
t
7 ns. Guaranteed by design.
Note 2:
t
CTp
is the first parameter on the input signal list.
Note 3:
Generated asynchronous to CTTL as a function of the inputs AD0–15, A16–23, and ADS.
Note 4:
Assuming MA1–15 load
l
RAS load.
Note 5:
Guaranteed by characterization. Due to tester conditions, these parameters are not 100% tested.
71
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