參數(shù)資料
型號(hào)： NS32FX100VF
廠(chǎng)商： National Semiconductor Corporation
英文描述： System Controller
中文描述： 系統(tǒng)控制器
文件頁(yè)數(shù)： 65/94頁(yè)
文件大小： 955K
代理商： NS32FX100VF
4.0 Device Specifications
(Continued)
4.2 OUTPUT SIGNAL LEVELS
The following tables show the levels of the NS32FX100 output control signals during reset or power save mode.
4.2.1 Freeze Mode Output Signals
Output signals are driven during Freeze mode (states S3,
S4, S5) as follows:
Name
Output Level
@
S3, S4, S5
*
Special
Features
CWAIT
HOLD
MA1–15
WE0–1
OE
SEL0
SEL1
SEL3
RAS0–1
CAS
SMPH0–3
PMPH0–3
PORT-B
PDO
BUZCLK
WDT
INTR
PEXT
CCLK
AD0–15
A16–23
ADS
DDIN
PORT-C
SDOUT
SDFDBK
SOSCO
FOSCO
TRI-STATE
TRI-STATE
Drive Low
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
Toggle/drive low
**
Toggle/drive low
**
TRI-STATE
TRI-STATE
T.S. according PBEN bit
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
Drive Low
***
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
T.S. according PCENx
Drive Low
****
Drive Low
****
Toggles
Drive High
V
OL
k
0.2V
*
2 Source T.S.
CMOS
CMOS
*
When MA1–15, CAS, RAS0 and RAS1 are driven low, their voltages
are below GND
a
0.2V, if less than 0.1 mA is driven.
**
When refresh is enabled, these signals are toggled. When refresh is
disabled, these signals are driven low.
***
When entering Freeze mode from full frequency.
****
MCFG
e
H’80
4.2.2 Reset/Power Restore Output Signals
During state S6 of the Power Save mode, output signals are
driven or floated either when reset is active or throughout
the S6 state. Output signals are driven during S6 as follows:
Name
Output Level
@
S6
*
Special
Features
CWAIT
HOLD
MA1–15
WE0–1
OE
SEL0
SEL1
SEL3
RAS0–1
CAS
SMPH0–3
PMPH0–3
PORT-B
PDO
BUZCLK
WDT
INTR
PEXT
CCLK
AD0–15
A16–23
ADS
DDIN
PORT-C
SDOUT
SDFDBK
FOSCO
SOSCO
Drive High
Drive High
Drive Low
Drive High
Drive High
Drive High
Drive High
Drive High
ToggleDrefresh
ToggleDrefresh
Drive Low
Drive Low
TRI-STATE
Undefined
Drive Low
Drive Low
Drive High
Drive High
Toggles
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
Drive
Drive
Toggles
Toggles
V
OL
k
0.2V
**
CMOS Level
2 Source T.S.
CMOS
CMOS
*
When RST is active and PFAIL is non-active (PFAIL
e
1, RST
e
0)
**
When MA1–15, CAS, RAS0 and RAS1 are driven low, their voltages are
below GND
a
0.2V, if less than 0.1 mA is driven.
65
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